12-11-2012, 05:00 PM
Integrated Precision Battery Sensor for Automotive ADuC7034
ADuC7034.pdf (Size: 1.9 MB / Downloads: 35)
VOLTAGE/TEMPERATURE CHANNEL ADC (V-/T-ADC)
The voltage/temperature channel ADC (V-/T-ADC) converts additional battery parameters, such as voltage and temperature. The input to this channel can be multiplexed from one of three input sources, namely, an external voltage, an external tempera-ture sensor circuit, or an on-chip temperature sensor.
As with the current channel ADC (I-ADC), the V-/T-ADC employs an identical Σ-Δ conversion technique, including a modified sinc3 low-pass filter to provide a valid 16-bit data conversion result at programmable output rates from 4 Hz to 8 kHz. An external RC filter network is not required because it is internally implemented in the voltage channel.
The external battery voltage (VBAT) is routed to the ADC input via an on-chip high voltage (divide-by-24) resistive attenuator. The voltage attenuator buffers are automatically enabled when the voltage attenuator input is selected.
The battery temperature can be derived through the on-chip temperature sensor or an external temperature sensor input. The time to a first valid (fully settled) result after an input channel switch on the voltage/temperature channel is three ADC conversion cycles with chop mode disabled.
ADC GROUND SWITCH
The ADuC7034 features an integrated ground switch pin, GND_SW (Pin 15). This switch allows the user to dynamically disconnect the ground from external devices and instead use either a direct connection to ground or a connection to ground via a 20 kΩ resistor. If the latter option is chosen, the additional resistor can be used to reduce the number of external components required for an NTC circuit. In addition, the ground switch feature can be used to reduce power consumption on application-specific boards.
ADC MMR INTERFACE
The ADC is controlled and configured through several MMRs that are described in detail in the ADC Status Register to Low Power Voltage Reference Scaling Factor Registersections.
All bits defined in the top eight MSBs (Bits[15:8]) of the ADCSTA MMR are used as flags only and do not generate interrupts. All bits defined in the lower eight LSBs (Bits[7:0]) of this MMR are logic OR’ed to produce a single ADC interrupt to the MCU core. In response to an ADC interrupt, user code should interrogate the ADCSTA MMR to determine the source of the interrupt. Each ADC interrupt source can be individually masked via the ADCMSKI MMR described in ADC Interrupt Mask Register section.
All ADC result ready bits are cleared by a read of the ADC0DAT MMR. If the current channel ADC is not enabled, all ADC result ready bits are cleared by a read of the ADC1DAT or ADC2DAT MMR. To ensure that I-ADC and V-/T-ADC conversion data are synchronous, user code should first read