26-06-2012, 01:10 PM
Interfacing and Applications of DSP Processor
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Introduction:
In the case of parallel peripheral interface, the data word will be
transferred with all the bits together. In addition to parallel peripheral interface, there is a
need for interfacing serial peripherals. DSP has provision of interfacing serial devices
too.
Synchronous Serial Interface:
There are certain I/O devices which handle transfer
of one bit at a time. Such devices are referred to as serial I/O devices or peripherals.
Communication with serial peripherals can be synchronous, with processor clock as
reference or it can be asynchronous. Synchronous serial interface (SSI) makes
communication a fast serial communication and asynchronous mode of communication is
slow serial communication. However, in comparison with parallel peripheral interface,
the SSI is slow. The time taken depends on the number of bits in the data word.
8.3 CODEC Interface Circuit: CODEC, a coder-decoder is an example for synchronous
serial I/O. It has analog input-output, ADC and DAC. The signals in SSI generated by the
DSP are DX:
Data Transmit to CODEC, DR: Data Receive from CODEC, CLKX:
Transmit data with this clock reference, CLKR: Receive data with this clock reference,
FSX: Frame sync signal for transmit, FSR: Frame sync signal for receive, First bit, during
transmission or reception, is in sync with these signals, RRDY: indicator for receiving all
bits of data and XRDY: indicator for transmitting all bits of data.
Similarly, on the CODEC side, signals are FS*: Frame sync signal, DIN: Data
Receive from DSP, DOUT: Data Transmit to DSP and SCLK: Tx / Rx data with this
clock reference. The block diagram depicting the interface between TMS320C54xx and
CODEC is shown in fig. 8.1. As only one signal each is available on CODEC for clock
and frame synchronization, the related DSP side signals are connected together to clock
and frame sync signals on CODEC. Fig. 8.2 and fig. 8.3 show the timings for receive and
transmit in SSI, respectively.
As shown, the receiving or transmit activity is initiated at the rising edge of clock, CLKR
receive data word depends on the number of bits in the data word. An example of data
to analog signal. Interpolation increases the sampling rate back to original value. LPF
smoothens the analog reconstructed signal by removing high frequency components.
The Serial Interface monitors serial data transfer. It accepts built-in ADC output and
converts to serial data and transmits the same on DOUT. It also accepts serial data on
DIN & gives the same to DAC. The serial interface works in synchronization with
BCLKIN & LRCIN. The Mode Control initializes the serial data transfer. It sets all the
desired modes, the number of bits and the mode Control Signals, MD, MC and ML. MD
carries Mode Word. MC is the mode Clock Signal. MD to be loaded is sent with
reference to this clock. ML is the mode Load Signal. It defines start and end of latching
bits into CODEC device.
Figure 8.5 shows interfacing of PCM3002 to DSP in DSK. DSP is connected to
PCM3002 through McBSP2. The same port can be connected to HPI. Mux selects one
among these two based on CPLD signal. CPLD in Interface also provides system clock
for DSP and for CODEC, Mode control signals for CODEC. CPLD generates BCLKIN
and LRCIN signals required for serial interface.