13-02-2013, 10:37 AM
Introduction To VIRTEX II Architecture
Introduction.ppt (Size: 1.42 MB / Downloads: 22)
Xilinx Architecture features
High performance at 2.5, 3.3V and 5V
Technology Independence
EDIF, VHDL, Verilog, SDF Interface
Footprint compatibility
Devices with each family are compatible with each other
Pin locking
VIRTEX
Up to 2 Million System Gates at 100+ MHz
Features:
Distributed and Block RAM available
Low Power
Delay Logic Loops
2.5V Internal Operation with support of common power
CLB Resources
Basic resource unit is the Logic Cell
1 CLB contains 2 - 4 Logic Cells, depending on device family
Logic Cell = 4-input Look-Up Table (LUT) + D Flip-flop
LUT capacity limited by number of inputs, not complexity of function
LUTs can be used as ROM or synchronous RAM
Flip-flop can be configured as a transparent latch in Virtex and Spartan-II
Simplified SLICE Structure
Each Slice has four outputs:
Two registered outputs
Two non-registered outputs
Two BUFTs associated, accessible by all 16 CLB outputs
Carry Logic for fast addition
Two independent carry chain per CLB
Fast Carry Logic
Each CLB contains separate logic and routing for the fast generation of carry signals
Increases efficiency and performance of adders, subtractors, accumulators, comparators, and counters
Carry logic is independent of normal logic and routing resources