29-05-2013, 04:18 PM
Introduction to Accumulators and FPGAs
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Introduction
This lab will introduce concepts of arithmetic circuits by introducing adders and accumulators. We
will also introduce basic concepts on FPGAs. We will develop an adder by means of hierarchical,
iterative design. The final system will be divided into subsystems or modules described on
independent VHDL files. We will also expand the concepts learned in previous labs to create,
synthesize and download a CPLD project; to FPGAs.
Design Description : Accumulator
The accumulator we will design must:
• Have a four bits wide synchronous input.
• Have an eight bit wide output which will be displayed using one out of four seven
segment digit displays available in the board.
• Includes reset capabilities.
• Must include a way to signal the system when a new input is ready to be read.
Design Analysis
A basic half adder logic diagram is shown in figure 1, including its equations and truth table. It is
called a half adder because it does not include a “carry in” within its inputs. Note that the circuit is
made of simple XOR and AND gates. A basic full adder logic diagram is shown in figure 2,
including its truth table. A full adder does include the “carry in” as an input. It is build by two half
adders and an additional OR gate. Note that figure 2 is showing a full 1 bit adder. In order to build
full X-bit adders (where X represents any integer) we must put together several 1-bit full adders.
There are several ways to do so. In this lab we will follow a “ripple carry adder” approach. A full 4-
bit adder schematic is shown in figure 3.
Adding a Clock Buffer
As seen in the previous step, the button used as a clock signal generator introduces more than
one clock edge each time it is pressed. To prevent this from happening, we’ll create a
button2clock block that will act as a buffer for the clock signal, thus eliminating the redundant
clock edges.
A block diagram for the buffer is shown in figure 20. Block 1 is a state machine described on
figure 21. The state machine will wait in state A until a rising edge is detected from the btn signal
(button activated by the user). Then the machine switches to state B and sends a signal called
run_i. The state machine will stay at state B until a rising edge is detected from a signal called
stop_i.