13-02-2013, 03:21 PM
JFET BIASING
JFET BIASING.docx (Size: 81.72 KB / Downloads: 18)
Aim:
- To design a circuit for source self-bias and voltage divider bias for the given Junction Field Effect Transistor Q-point (VDS = 5V, ID = 2mA, VGS = -2V).
Procedure: -
1) Components were tested and connected as per the circuit diagram.
2) VCC was set to 10V using power supply.
3) Multimeter was used to measure VDD,G , VD,G and VS,G. The values of ID and VDS were computed.
4) The procedure was repeated for voltage divider circuit.