10-04-2014, 12:57 PM
LOW LEAKAGE NANOSCALED SOURCE AND DRAIN OVER INSULATOR FINFET WITH UNDERLAP AND HIGH K DIELECTRIC
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Abstract:
In this paper a Source and drain over Insulator (SDOI) FinFET structure in which S/D regions insulated from
body by buried oxide with undoped underlap and Si3N4 as dielectric is studied and compared with SDOI FinFET
with SiO2 as dielectric. An extensive simulation study and analysis of the effect of underlaps on SDOI FinFET
has been performed using the TCAD Silvaco (DevEDIT, ATLAS). The simulations have revealed that the SDOI
FinFET structures with underlaps and Si3N4 as dielectric improves short channel effect significantly.
Introduction
THE miniaturization of the device dimensions has been historically used to improve the performance of bulk
CMOS devices. The scaling of MOSFET dimensions has led to increased speed, high drivability, chips with
increased functionality, and reduced cost [1], [2]. The era of bulk MOSFET, however, is nearing its end. The
continuation of scaling of bulk MOSFET in the nanometer range (<65 nm) has become extremely difficult as
the performance of bulk MOSFET is severely degraded by short channel effects (SCEs). The most important
SCEs include drain-induced barrier lowering (DIBL), threshold voltage roll off problem, increase in gate
leakage current, mobility degradation, etc. When the channel length shrinks, the gate control over the channel
reduces due to various SCEs, such as DIBL, charge sharing, and subsurface punch through [3]. In such a
scenario, the thin-film silicon-on-insulator (SOI)-based MOSFET looks set to become the next driver for CMOS
scaling. SOI technology is capable of providing increased transistor speed, reduced power consumption, low
leakage power, near-ideal isolation between devices, significant reduction in parasitic capacitance, and extended
scalability. A significant reduction in SCEs and a steeper subthreshold slope are obtained in the thin-film SOI-
based MOSFET. SOI has also become a substrate of choice for SOI-BiCMOS technology for efficient
realization of system-on-chip[4,5,6].
Simulation Results
The schematic structure of the device under condition is given in the Fig. 2. In case of the SDOI FinFET , a
localized insulator is introduced at the bottom of the source and drain region which provides better heat
dissipation path. Complete 3D simulations of the devices were performed using Silvaco DevEDIT (3D), Atlas
TCAD software. A self-consistent Schrodinger-Poisson with Bohm Quantum Potential model (BQP) [22] is
used for the simulations. The various models used in this study are fldmob, hcte, srh, fermi and bqp. The
mobility model fldmob specifies that parallel electric field is used. The conventional drift-diffusion model of
charge transport neglects non-local effects, such as velocity overshoot and reduced energy dependent impact
ionization. These effects are incorporated in this study by using an energy balance model, which uses a higher
order approximation of the Boltzmann Transport Equation. Since recombination effects are important, therefore,
the concentration dependent Shockley–Read–Hall model (consrh) and Auger recombination model (auger) are
activated in simulations. Similarly, we used Fermi-Dirac statistics for the simulation.
Short Channel Effects (SCEs)
The silicon fin thickness, gate oxide thickness, BOX thickness, junction depth, and channel length are the
important parts of the device from an electrostatic point of view to control threshold voltage roll-off, DIBL, and
subthreshold swing. The main SCEs are the threshold voltage roll-off due to charge sharing, the degradation of
subthreshold swing(S), and the Drain induced barrier lowering(DIBL). These effects result in an increase in the
OFF current (IOFF), decrease in threshold voltage (Vth) and the deterioration of the ON–OFF current ratio (ION/
IOFF). Electrostatic integrity relates both DIBL and threshold voltage roll-off SCE and describes the quality of
electrostatic control of the channel by the gate.
Conclusion
A 3-D simulation of SDOI FinFET device with underlap and spacers of SiO2 and Si3N4 has been performed. The
incorporation of underlap with SDOI FinFET device and with Si3N4 as dielectric has resulted in a significant
improvement in SCEs i.e. DIBL reduces by 11.43%, leakage current reduces by 44% and ION/IOFF increases by
76.7% when Si3N4 is used in place of SiO2 as spacers. The use of Si3N4 instead of SiO2 increases ION by 34%.
The reduction in leakage current reduces power dissipation. This avoids heating, increases lifetime and
ultimately the reliability of the device.