14-10-2016, 01:44 PM
LOW-TRANSITION TEST PATTERN GENERATION FOR MINIMIZING TEST POWER IN VLSI CIRCUITS USING BIST TECHNIQUE
1459006204-IJIREEICE2HapraveenLOWTRANSITIONTESTPATTERNGENERATIONFORMINIMIZINGTESTPOWERINVLSICIRCUITSUSINGBIST.pdf (Size: 504.94 KB / Downloads: 5)
Abstract: Any Integrated circuit (IC) manufactured by the semiconductor manufacturing company contains test circuit
and the circuit under test (CUT). The test circuit is used to test the correct functionality of the CUT and which is called
Built In Self Test (BIST). This Built In Self Test used to generate test vectors which are applied to the circuit under
test by inbuilt chip within an integrated circuit. In pseudorandom BIST design, the test vectors are generated in random
style by Linear Feedback Shift Registers (LFSR). The main drawback of these conventional LFSRs is, it generates
normally a number of random natured test vectors for testing the CUT in which many are repeated vectors and
application of which unnecessarily increase the test power without contributing much to the fault coverage also the
bulkiness of the CUT increases.
This paper presents a new approach, called Low Power -Bit complement test vector generation technique (LP-BCTVG).
In LP-BCTVG technique, the output bits are complemented due to which unreported test vectors are increasing also by
which better fault coverage with a reduction in the bulkiness of the test circuit can be achieved.
INTRODUCTION
Today‟s System-On-Chip (SOC) devices contain an
integration of a large number of processors, different types
of memories like SRAM, user defined logic and Digital
signal processors, with an increasing count in transistors
on a single chip thereby, challenging the design and
testing methodologies in vogue. The testing of ICs, today
mandates a new and high-level of competence and
accuracy, expecting complete verification through all of
the stages of the design process.
It is well-known fact that power dissipation in the circuit
during the test mode is considerable more compared to
that in the normal mode [1]. This can be admitted to the
correlation existing between consecutive test vectors
applied during the normal mode of operation of the
circuit.But, this is not the fact in the test mode. There is no
considerable coefficient of correlation between successive
vectors in the test mode. This automatically means that the
primary switching activities will be more in the test mode
compared to that in the normal mode and the power
dissipation will be higher in the test mode. Thus, more the
transitions between the test vectors more will be the power
dissipated. Hence, low power testing is the need of the
hour.
By using BIST test design this can be easily overcome. A
BIST design consists as a part of the target device that aids
in the confirmation of the internal functionality of the
exacting design for which it is assigned. BIST is a
technique of allowing test logic to be integrated with die
itself.
The BIST architecture is widely accepted because of its
very many advantages like the reduction in test application
time, reduction in the cost of generation of test vectors, to
allow at-speed testing, to provide an alternative to the
expensive Automatic Testing Equipment (ATE) and the
reduction in the volume of test data. Also, the overhead
area occupied by the BIST in the circuit can be considered
negligible in comparison to the size of the target system
[2]. The BIST makes the target system independent of any
external automatic equipment for testing [1].
Hence, this proposed method aims to analyze and discuss
a circuit that generates test patterns that help reduce the
average and peak power dissipation in BIST architecture
during testing mode. Also, efforts are made to bring about
appropriate modifications to the logical and structural
implementation, of the circuit under consideration, in
order to reduce the power dissipation even further.
2. TEST PATTERN GENERATION
The vectors in the test mode may consume higher average
or peak power than that in the normal mode. The
decreased coefficient correlation between the
pseudorandom patterns (the patterns generated will repeat
after a cycle is completed) generated by the LFSR is
credited as the reason for the additional dissipated power
in test mode. This in turn ends in an increase in the
switching actions of the circuit, thereby, causes to
increased power dissipation
Need for low power testing
The System-On-Chips platform imposes a challenge in the
design and testing methodology. Testing gains the primary
significance in terms of issues and expenditure, thereby,
demanding a wide range of possible novelties. The area of
concentration, here, is power dissipation [1]. In general,
the power consumed during the test mode is more than
that in the normal mode of operation. This additional
power dissipated may pose a threat to the circuitry and can
also lead to a breakdown of the chip. This in turns will
raise the costs, increase the difficulty in verifying the
performance of the circuit and thereby reduce the final
code [1]. Having learnt the above, the necessity of
decreasing the power dissipated in a circuit during the test
mode is a major milestone for further advancements in
VLSI design.
A number of reasons can be quoted for the increased
power consumption in the circuit during the test mode [2].
Decreased correlation between the test vectors can be sited
as the first reason. Normally, a considerable correlation
exists between the inputs during the operational mode, but
may not be the same in the test mode. This decreased
correlation in the input during the test mode increases the
switching activities, thereby increasing the power
dissipation [1]. Secondly, the use of parallel testing
process by test engineers in order to reduce the test
application time can result in increased power dissipation.
The third reason can be attributed to the DFT circuit that is
inbuilt in the design for the test mode, which is normally
idle during the operational mode, however, is extensively
active in the test mode [2].
2.2 Reviews of Low Power BIST Models
The low power BIST issue can be tackled by designing a
DFT using various techniques. The increase in the number
of components and functional units in a single chip
automatically means an increase in the testing difficulties.
Described below a few methods designed to tackle and
reduce the power dissipation during test mode. Dual speed
LFSR (DS-LFSR) is the proposed model in [5] which aids
in decreasing the heat dissipated during the test process.
Here, two LFSR‟s, a slow LFSR and a normal speed
LFSR are used. A slower clock speed is used for the slow
LFSR compared to that of the normal speed LFSR. This
reduces the transition density at the inputs which, in turn, reduces the heat dissipation. The increase in the number of
vectors accomplishes increased fault coverage proportion
by generating patterns that are distinctive and evenly
distributed. Also, further heat dissipation is reduced by
combining compatible inputs with the inputs of slow
LFSR in order to increase the number of inputs.
In the method adopted in [6], a test - per - clock
architecture model is designed which modifies the
conventional LFSR to generate low power patterns. In this
scheme, two clocks, which are in synchronies with a
Master clock, are used. Both clocks have a speed that is
half of that of a normal clock speed. During one clock
cycle, one of the clocks is used to activate one half of the
D flip flops and for the next clock cycle, the other clock is
used to activate the second half of the D flip flops. The
same management is executed for the clock that feeds the
Test Pattern Generator as well. The fault coverage and the
testing time remain the same as that of a standard BIST
model and the area overhead is almost negligible.
The test pattern generator algorithm described in [7] is the
Non-Linear Hybrid Cellular automata for testing, based on
Cellular Automata for reducing power dissipation and
increasing fault coverage ratio at the same time. Here
again, the test – per – clock design has been adopted,
wherein, the main outputs are monitored by an Output
Data Analyzer (ODA) and the primary inputs are fed by a
Hybrid Cellular Automaton (HCA). The Cellular
Automata generates low power test vectors. This model
proposes two main goals; namely, to reduce power
dissipation during the test mode and give the required fault
coverage ratio for the respective test patterns. However,
the area overhead remains the same as for a normal BIST
architecture. Because of the good statistical properties, the
Cellular Automata scheme is considered a very attractive
option for Test Pattern Generation [14].
The BIST model designed in [8] is a scheduling process of
the BIST that considers constraints like the power
dissipation, area overhead, noise, etc. That implements the
BIST architecture with a highly modular architecture and
thereby, introduces a new BIST control methodology. The
BIST scheme and the BIST control elements are
independent of each other because of the uniformity of the
interface. For the Power dissipation Analysis, the clock
speed is considered at the normal system clock speed to
obtain all of the advantages, though a clock speed lower
than the system speed will prevent excessive power
dissipation due to the increased activity rate. Also,
optimization is achieved by sharing the BIST strategy with
other groups of the same type that are actually identical
but may have their parameters differ.
The Low Power/Energy BIST scheme for Data paths
designed in [9] is proposed based on the fact that power
consumption by functional modules, like multipliers, of
the datapath is huge. Hence, a Low Power BIST
architecture for data paths created along the multiplier –
accumulator pairs are considered. This model relies on test
patterns that are deterministic. In this case, two schemes
are proposed, wherein, one relies on reduced power
dissipation during the BIST procedure and the other relies
on reduced power dissipation between consecutive test
patterns. The former scheme depends on compact test
patterns generated by a counter – based Test Pattern
Generator which is of fixed size. This causes a very low
primary input switching activity, which in turn lower the
energy consumption. Since the area overhead and the
efficiency are far better, it is much compatible and
effective with portable devices. The latter scheme depends
on the linear – sized test patterns and is highly reliable in
reducing average energy consumption among test vectors.
Search depending on genetic algorithm, in order
establishes signal probabilities, to decrease power
consumption, called the POWETEST, is modeled in [10].
This model targets for portable and wireless applications,
where power consumption is the primary concern. A
random pattern generation using weighted average is the
mode of operation here. The procedure depends on
controllability and observability measure depending on the
probability that the main input signal is logic „1‟ and this
aids the testability of a circuit. The relevant inputs to the
primary node are provided either by an LFSR or a Cellular
Automata. Controllability is a measure of the difficulty of
setting a particular node to a logic „1‟ or logic „0‟ from the
primary input and Observability is a measure of difficulty
in observing a particular node from the primary output.
The test vector inhibiting technique in [11] helps in
reduced power dissipation by generating the least number