18-12-2012, 05:29 PM
Latches and Flip-Flops
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Latches and Flip-Flops
Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit of
information. The main difference between latches and flip-flops is that for latches, their outputs are constantly
affected by their inputs as long as the enable signal is asserted. In other words, when they are enabled, their content
changes immediately when their inputs change. Flip-flops, on the other hand, have their content change only either
at the rising or falling edge of the enable signal. This enable signal is usually the controlling clock signal. After the
rising or falling edge of the clock, the flip-flop content remains constant even if the input changes.
There are basically four main types of latches and flip-flops: SR, D, JK, and T. The major differences in these
flip-flop types are the number of inputs they have and how they change state. For each type, there are also different
variations that enhance their operations. In this chapter, we will look at the operations of the various latches and flipflops.
Bistable Element
The simplest sequential circuit or storage element is a bistable element, which is constructed with two inverters
connected sequentially in a loop as shown in Figure 1. It has no inputs and two outputs labeled Q and Q’. Since the
circuit has no inputs, we cannot change the values of Q and Q’. However, Q will take on whatever value it happens
to be when the circuit is first powered up. Assume that Q = 0 when we switch on the power. Since Q is also the
input to the bottom inverter, Q’, therefore, is a 1. A 1 going to the input of the top inverter will produce a 0 at the
output Q, which is what we started off with. Similarly, if we start the circuit with Q = 1, we will get Q’ = 0, and
again we get a stable situation.
A bistable element has memory in the sense that it can remember the content (or state) of the circuit
indefinitely. Using the signal Q as the state variable to describe the state of the circuit, we can say that the circuit has
two stable states: Q = 0, and Q = 1; hence the name “bistable.”
An analog analysis of a bistable element, however, reveals that it has three equilibrium points and not two as
found from the digital analysis. Assuming again that Q = 1, and we plot the output voltage (Vout1) versus the input
voltage (Vin1) of the top inverter, we get the solid line in Figure 2. The dotted line shows the operation of the bottom
inverter where Vout2 and Vin2 are the output and input voltages respectively for that inverter.
SR Latch
The bistable element is able to remember or store one bit of information. However, because it does not have any
inputs, we cannot change the information bit that is stored in it. In order to change the information bit, we need to
add inputs to the circuit. The simplest way to add inputs is to replace the two inverters with two NAND gates as
shown in Figure 4(a). This circuit is called a SR latch. In addition to the two outputs Q and Q', there are two inputs S'
and R' for set and reset respectively. Following the convention, the prime in S and R denotes that these inputs are
active low. The SR latch can be in one of two states: a set state when Q = 1, or a reset state when Q = 0.
To make the SR latch go to the set state, we simply assert the S' input by setting it to 0. Remember that 0 NAND
anything gives a 1, hence Q = 1 and the latch is set. If R' is not asserted (R' = 1), then the output of the bottom NAND
gate will give a 0, and so Q' = 0. This situation is shown in Figure 4 (d) at time t0. If we de-assert S' so that S' = R' =
1, the latch will remain at the set state because Q', the second input to the top NAND gate, is 0 which will keep Q = 1
as shown at time t1. At time t2 we reset the latch by making R' = 0. Now, Q' goes to 1 and this will force Q to go to a
0. If we de-assert R' so that again we have S' = R' = 1, this time the latch will remain at the reset state as shown at
time t3. Notice the two times (at t1 and t3) when both S' and R' are de-asserted.
SR Latch with Enable
The SR latch is sensitive to its inputs all the time. It is sometimes useful to be able to disable the inputs. The SR
latch with enable (also known as a gated SR latch) accomplishes this by adding an enable input, E, to the original
implementation of the latch that allows the latch to be enabled or disabled. The circuit for the SR latch with enable
using NAND gates is shown in Figure 6(a), its truth table in Figure 6(b), and logic symbol in Figure 6©. When E =
1, the circuit behaves like the normal NAND implementation of the SR latch except that the S and R inputs are active
high rather than low. When E = 0, the latch remains in its previous state regardless of the S and R inputs. In actual
circuits, the enable input can either be active high or low, and may be named ENABLE, CLK, or CONTROL. A typical
operation of the latch is shown in the timing diagram in Figure 6(d). Between t0 and t1, E = 0 so changing the S and R
inputs do not affect the output. Between t1 and t2, E = 1 and the trace is similar to the trace of Figure 4(d) except that
the input signals are inverted.
Latch with Enable
Just like the SR latch with an enable input, the D latch can also have an enable input as shown in Figure 9(a).
When the E input is asserted (E = 1), the Q output follows the D input. In this situation, the latch is said to be “open”
and the path from the input D to the output Q is “transparent”. Hence the circuit is often referred to as a transparent
latch. When E is de-asserted (E = 0), the latch is disabled or “closed”, and the Q output retains its last value
independent of the D input. A sample timing diagram for the operation of the D latch with enable is shown in Figure
9(d). Between t0 and t1, the latch is enabled with E = 1 so the output Q follows the input D. Between t1 and t2, the
latch is disabled, so Q remains stable even when D changes.
Flip-Flop
Latches are often called level-sensitive because their output follows their inputs as long as they are enabled.
They are transparent during this entire time when the enable signal is asserted. There are situations when it is more
useful to have the output change only at the rising or falling edge of the enable signal. This enable signal is usually
the controlling clock signal. Thus, we can have all changes synchronized to the rising or falling edge of the clock.
An edge-triggered flip-flop achieves this by combining in series a pair of latches. Figure 10(a) shows a positiveedge-
triggered D flip-flop where two D latches are connected in series and a clock signal Clk is connected to the E
input of the latches, one directly, and one through an inverter. The first latch is called the master latch. The master
latch is enabled when Clk = 0 and follows the primary input D. When Clk is a 1, the master latch is disabled but the
second latch, called the slave latch, is enabled so that the output from the master latch is transferred to the slave
latch.