12-10-2016, 04:24 PM
1458838693-LiteratureSurveyonDeadlocksinNetwork.docx (Size: 12.26 KB / Downloads: 6)
Introduction:
network on chip (NoC) refers to distributed connectivity of computing and other resources that are configured as an on-chip computer network. At sub-32-nanometer dimensions, increased electrical noise and cross-talk reduces the effectiveness of traditional on-chip bus structures. Complex system-on-chip (SoC) devices will require a network-like structure with an error correction protocol. The most likely topology will be a globally asynchronous locally synchronous (GALS) structure. NoC technology applies networking theory and methods to on-chip communication and brings notable improvements over conventional bus and crossbar interconnections. NoC improves the scalability of SoCs, and the power efficiency of complex SoCs compared to other designs.
Many challenging research problems remain to be solved at in Networks on Chips (NoCs). Removing deadlocks in Networks on Chips (NoCs) with is a major challenge.
In this Survey Project we present the methods to detect and avoid the deadlock in Networks-on chips and their algorithm. To determine that a network in chip is deadlock free or not, channel dependency graph is used. which counts the number of cycles in network in chips.