22-01-2013, 12:19 PM
Logic Design for On-Chip Test Clock Generation- Implementation Details and Impact on Delay Test Quality
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Abstract
Thispaper addresses delay testfor SOC devices with
highfrequency clock domains. A logic design for onchip
high-speed clock generation, implemented to
avoid expensive test equipment, is described in
detail. Techniques for on-chip clock generation,
meant to reduce test vector count and to increase test
quality, are discussed. ATPG results for the
proposed techniques are given.
Introduction
Structural testing of digital integrated circuits already
has a long tradition in the semiconductor industry.
Scan test in combination with automatic test pattern
generation (ATPG) for stuck-at and test have
been the industry standard for many years. Scan
based ATPG for structural at-speed test, or delay
test, is also well known for about 20 years based on
the gate delay fault model path delay fault model
and transition fault model
Many publications show that at-speed test is able to
detect production defects that are not covered by
static tests, Functional at-speed tests
require a significant effort to develop compared to
delay tests that are automatically generated by ATPG
tools. Moreover, delay tests have a known fault
coverage because of the usage of ATPG tools. Fault
grading is difficult to impossible for functional atspeed
tests. Thus, the fault coverage for functional
at-speed tests usually remains unknown.
Delay Test for State-of-the-ArtSOCdevices
Delay test is a two-vector (cycle) test. The first
vector initializes the test. The second vector launches
the desired transition at the source of a path under
test and propagates the launched transition to an
observation point. Test responses are captured with
the next active clock edge at the observation point.
Thus, test frequency requirements between initial
and launch vector are relaxed, while the clock
between launch and capture has to be operated at the
functional speed of the device under test (DUT).
Delay Test ATPG
Delay test ATPG has to consider at least two
consecutive clock cycles, as delay test is a
vector test. Due to the sequential nature of the ATPG
problem, delay test ATPG is more complex than
stuck-at ATPG. The use of more than one clock
cycle during ATPG is already known for stuck-at
ATPG. Additional clock cycles are used to initialize
sequential elements such as non-scan cells and
- known as “clock sequential” and “RAM
sequential ATPG, respectively. This adds even
more complexity to the delay fault ATPG problem.
But especially access to is important for delay
testing as critical functional timing paths frequently
involve functional paths .
Conclusions
Even though delay defects become increasingly
important for new technologies, high-speed testers
are hardly affordable for SOC devices targeting
consumer products. Therefore, high-speed on-chip
clock generation for delay testing is one cornerstone
of SOC test strategies.
For the device under investigation the transition test
coverage is reduced by more than 7% when simple
two-pulse on-chip clock generation is implemented.
Moreover, increased pattern count requires a more
extensive use of an on-chip technique to reduce scan
chain length. Only using this technique the observed
pattern count can be loaded into the ATE vector
memory without truncation of the test pattern set.
Experiments have shown that enhancements in onchip
clock generation capabilities improve the test
coverage and reduce the pattern count. To achieve
further improvements work will focus on two
main objectives.