01-01-2013, 10:35 AM
Logic Synthesis for Large Pass Transistor Circuit
1Logic Synthesis.pdf (Size: 85.86 KB / Downloads: 20)
Abstract
Pass transistor logic (PTL) can be a promising alternative to static
CMOS for deep sub-micron design. In this work, we motivate the need for
CAD algorithms for PTL circuit design and propose decomposed BDDs
as a suitable logic level representation for synthesis of PTL networks.
Decomposed BDDs can represent large, arbitrary functions as a multistage
circuit and can exploit the natural, efficient mapping of a BDD to
PTL.
A comprehensive synthesis flow based on decomposed BDDs is outlined
for PTL design. We show that the proposed approach allows us to
make logic-level optimizations similar to the traditional multi-level network
based synthesis flow for static CMOS, and also makes possible optimizations
with a direct impact on area, delay and power of the final
circuit implementation which do not have any equivalent in the traditional
approach. We also present a set of heuristical algorithms to synthesize
PTL circuits optimized for area, delay and power which are key to the
proposed synthesis flow.
Experimental results on ISCAS benchmark circuits show that our
technique yields PTL circuits with substantial improvements over static
CMOS designs. In addition, to the best of our knowledge this is the first
time PTL circuits have been synthesized for the entire ISCAS benchmark
set.
Introduction
Static CMOS has long been the design style of choice for IC
designers due to the ease of designing safe, scalable circuits.
However, switching capacitances in a static CMOS circuit can be
fairly large. With the shrinking feature sizes and increasing transistor
counts on chips, the push for higher speed and lower power
makes it necessary to look for alternative design styles which can
offer better performance characteristics to static CMOS. These
include pass-transistor-based logic families, domino-like
dynamic logic styles etc.
Among these, pass transistor logic (PTL) circuits offer great
promise. Compared to domino circuits, they are less susceptible
to crosstalk problems, which is a major issue in deep sub-micron
technology. Several case studies ([4][21]) have shown that PTL
can implement most functions with fewer transistors than static
CMOS. This reduces the overall capacitance, resulting in faster
switching times and lower power. It was reported in [21] that a
complementary PTL multiplier was twice as fast as conventional
CMOS due to lower input capacitance and higher logic functionality.
At a supply voltage of 4V, PTL designs typically consume
30% less power than static CMOS designs ([5]). To illustrate this
point, we take a function F = A’+BC’. Fig. 1(a) shows our implementation
of this function in PTL and Fig. 1(b) shows the corresponding
static CMOS implementation. Clearly, the PTL design
style can yield a circuit which can be much more compact than
static CMOS. It was reported in [22] that the PTL yielded a 32%
improvement in area, 29% improvement in delay and a 47%
improvement in power over a static CMOS OR/NAND-based
implementation of this function.
PTL Networks and BDDs
One of the main strengths of static CMOS designs is that they are
guaranteed to not have a steady-state sneak path connecting a
node to both power supply and ground at the same time under
some input combination. From Section 1, PTL admits more general
circuit structures than static CMOS. However, it suffers from
the drawback that there is no guarantee on the absence of sneak
paths in the circuit. Hence, special care needs to be taken to
ensure that the circuit is sneak path-free. For example, the PTL
circuit in Fig. 2 requires only three transistors to implement the
example function from Fig. 1. However, this circuit has a sneak
path as shown, forcing the output to be connected to both ground
and power supply at the same time when A=1, B=0, C=0. We
therefore need a methodology to synthesize PTL circuits which
ensure the absence of such sneak paths.
PTL Networks and Decomposed BDDs
We propose a synthesis approach which does not construct monolithic
BDDs for the circuit at all. The common problem of the previous
works outlined in Section 2 is that they try to improve a
monolithic BDD-based solution. Our approach is truly multistage
in that we always work with a multi-level representation of
the PTL circuit which is similar to the traditional multi-level network
for static CMOS. For such a flow, we propose decomposed
BDDs as a suitable logic level abstraction of the circuit which
exploits the correspondence between PTL circuits and BDDs
without suffering from the drawbacks imposed by properties of
monolithic BDDs which may be useful for logic level data representation
but are unnecessary for circuit generation (e.g. canonicity).
A Synthesis Flow for PTL Design
Apart from proposing a decomposed BDD-based representation
for PTL synthesis, a major contribution of this work is a comprehensive
synthesis flow for PTL design.
Fig. 7 outlines the key steps of the traditional multi-level network
based synthesis flow for static CMOS. We propose an analogous
synthesis flow where a decomposed BDD is used to
represent a circuit similar to the multi-level network in the traditional
flow and each decomposition point BDD is manipulated
similar to a complex node in the multi-level network.
A big advantage of the BDD-based PTL network design is
that the one-to-one mapping between the BDD and the PTL network
makes the technology mapping problem very straightforward.
As a result, we can perform circuit level optimizations by
manipulating the BDD. The fact that mapping preserves the circuit
structure allows us to make high-level changes which can
have significant impact on area, power and performance, but for
which gains made at the high level hold at the circuit level as
well.
Low Power
Power dissipation in a circuit is a function of switching capacitance
and switching activity. It is thus desirable that the capacitance
connected to nodes with high switching activity is
minimized. Since the gate capacitance of a transistor is substantially
higher than the drain/source capacitances, this translates
into ensuring that the high switching activity nodes are not connected
to the gates of too many transistors. Note that neglecting
drain-source capacitance switching is analogous to ignoring the
internal node switching in a static CMOS gate.
In the case of PTL networks, only control variables are connected
to the gate terminals of transistors. In our decomposed
BDD-based approach, the control variables consist of primary
inputs and decomposition points. Note that every node in the
BDD is implemented as a multiplexer in the corresponding circuit
and the node variable in the BDD is connected to the gates of two
transistors of the multiplexer. Minimizing the occurrences of high
switching activity node then translates into minimizing the occurrences
of the corresponding variable in the BDD.
Results
The techniques described in this paper have been tested on
ISCAS benchmarks circuits, which include circuits which are
hard for monolithic BDD-based approaches (e.g. C6288). In the
following we present results comparing our PTL synthesis algorithm
with different static CMOS synthesis algorithms to demonstrate
the area and delay gains achieved by our approach, and
HSPICE simulations to verify the validity of the logic level gains.
The PTL synthesis algorithm was implemented in the SIS
framework. It is compared against four synthesis scripts for static
CMOS: area and delay optimization scripts which do not use
don’t cares, and script.rugged and script.delay of SIS. Technology
mapping was performed using three different libraries:
msu.genlib, 33-4.genlib, and 44-3.genlib. All experiments were
carried out on a 400 MHz DEC Alpha with a SPECint_92 rating
of 341, DEC 21164 CPU, 4Mb cache and 2Gb total memory.