06-03-2013, 04:52 PM
Memory Hierarchy Design
Memory Hierarchy.pptx (Size: 230.91 KB / Downloads: 21)
Basic Cache Read Operation
CPU requests contents of memory location
Check cache for this data
If present, get from cache (fast)
If not present, read required block from main memory to cache
Then deliver from cache to CPU
Cache includes tags to identify which block of main memory is in each cache slot
Elements of Cache Design
Cache size
Line (block) size
Number of caches
Mapping function
Block placement
Block identification
Replacement Algorithm
Write Policy
Line Size
Optimum size depends on workload
Small blocks do not use locality of reference principle
Larger blocks reduce the number of blocks
Replacement overhead
Practical sizes?
Number of Caches
Increased logic density => on-chip cache
Internal cache: level 1 (L1)
External cache: level 2 (L2)
Unified cache
Balances the load between instruction and data fetches
Only one cache needs to be designed / implemented
Split caches (data and instruction)
Pipelined, parallel architectures
Write Policy
Write is more complex than read
Write and tag comparison can not proceed simultaneously
Only a portion of the line has to be updated
Write policies
Write through – write to the cache and memory
Write back – write only to the cache (dirty bit)
Write miss:
Write allocate – load block on a write miss
No-write allocate – update directly in memory
Reducing Cache Misses
Causes of Misses: 3 Cs
Compulsory( Cold Start or First reference)
The very first access to a block cannot be in the cache, so the first block must be brought into the cache.
Capacity
If the cache cannot contain all the blocks needed during execution of a program, capacity misses will occur because of blocks being discarded and later retrieved
Conflict( Collision or Interference)
If the block placement strategy is set associative or direct mapped, conflict misses will occur because a block can be discarded and later retrieved if too many blocks map to its set.