27-11-2012, 01:28 PM
Metal Oxide Semiconductor Field Effect Transistors
1Metal Oxide.ppt (Size: 1.5 MB / Downloads: 100)
Basic MOSFET (n-channel)
The gate electrode is placed on top of a very thin insulating layer.
There are a pair of small n-type regions just under the drain & source electrodes.
If apply a +ve voltage to gate, will push away the ‘holes’ inside the p-type substrate and attracts the moveable electrons in the n-type regions under the source & drain electrodes.
Increasing the +ve gate voltage pushes the p-type holes further away and enlarges the thickness of the created channel.
As a result increases the amount of current which can go from source to drain — this is why this kind of transistor is called an enhancement mode device.
Basic MOSFET (p-channel)
These behave in a similar way, but they pass current when a -ve gate voltage creates an effective p-type channel layer under the insulator.
By swapping around p-type for n-type we can make pairs of transistors whose behaviour is similar except that all the signs of the voltages and currents are reversed.
Pairs of devices like this care called complimentary pairs.
In an n-channel MOSFET, the channel is made of n-type semiconductor, so the charges free to move along the channel are negatively charged (electrons).
In a p-channel device the free charges which move from end-to-end are positively charged (holes).
Structure and principle of operation
A top view of MOSFET, where the gate length, L, and gate width, W.
Note that L does not equal the physical dimension of the gate, but rather the distance between the source and drain regions underneath the gate.
The overlap between the gate and the source/drain region is required to ensure that the inversion layer forms a continuous conducting path between the source and drain region.
Typically this overlap is made as small as possible in order to minimize its parasitic capacitance.
New Gate Metal
The doped polycrystalline silicon used for gates has a very thin depletion layer, approximately 1 nm thick, which causes scaling problems for small devices.
Others metals are being investigated for replacing the silicon gates, including tungsten and molybdenum.
Removing the substrate: Silicon on Insulator (SOI)
For high-frequency circuits (about 5 GHz and above), capacitive coupling to the Si substrate limits the switching frequency.
Also, leakage into the substrate from the small devices can cause extra power dissipation.
These problems are being avoided by making circuits on insulating substrates (either sapphire or silicon dioxide) that have a thin, approximately 100 nm layer of crystalline silicon, in which the MOSFETs are fabricated.
Silicon on Insulator (SOI)
SOI — silicon on insulator, refers to placing a thin layer of silicon on top of an insulator such as SiO2.
The devices will be built on top of the thin layer of silicon.
The basic idea of SOI is to reduced the parasitic capacitance and hence faster switching speed.
Every time a transistor is turned on, it must first charge all of its internal (parasitic) capacitance before it can begin to conduct.
The time it takes to charge up and discharge (turn off) the parasitic capacitance is much longer than the actual turn on and off of the transistor.
If the parasitic capacitance can be reduced, the transistor can be switched faster — performance.
SOI CMOS
Silicon-on-insulator CMOS offers a 20–35% performance gain over bulk CMOS.
As the technology moves to the 0.13-µm generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs.
Some of the recent applications of SOI in high-end microprocessors and its upcoming uses in low-power, radio-frequency (rf) CMOS, embedded DRAM (EDRAM), and the integration of vertical SiGe bipolar devices on SOI are described.