25-07-2012, 12:13 PM
Microcontroller AT89S8253 (8-bit with 12 Kbyte Flash)
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Description
The AT89S8253 is a low-power, high-performance
CMOS 8-bit microcontroller with 12K bytes of In-
System Programmable (ISP) Flash program memory
and 2K bytes of EEPROM data memory. The device
is manufactured using Atmel’s high-density
nonvolatile memory technology and is compatible
with the industry-standard MCS-51 instruction set
and pinout. The on-chip downloadable Flash allows
the program memory to be reprogrammed in-system
through an SPI serial interface or by a conventional
nonvolatile memory programmer. By combining a
versatile 8-bit CPU with downloadable Flash on a
monolithic chip, the Atmel AT89S8253 is a powerful
microcontroller which provides a highly-flexible and
cost-effective solution to many embedded control
applications.
The AT89S8253 provides the following standard
features: 12K bytes of In-System Programmable
Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32
I/O lines, programmable watchdog timer,two data
pointers, three 16-bit timer/counters, a six-vector,
four-level interrupt architecture, a full duplex serial
port, on-chip oscillator, and clock circuitry. In
addition, the AT89S8253 is designed with static logic
for operation down to zero frequency and supports
two software selectable power saving modes. The
Idle Mode stops the CPU while allowing
the RAM, timer/counters,serial port, and interrupt
system to continue functioning. The Power-down
mode saves the RAM contents but freezes the
oscillator, disabling all other chip functions until the
next external interrupt or hardware reset.
The on-board Flash/EEPROM is accessible through
the SPI serial interface. Holding RESET active
forces the SPI bus into a serial programming
interface and allows the program memory to be
written to or read from, unless one or more lock bits
have been activated.
Pin Configurations
VCC
Supply voltage (all packages except 42-PDIP).
GND
Ground (all packages except 42-PDIP; for 42-PDIP
GND connects only the logic core and the
embedded program/data memories).
VDD
Supply voltage for the 42-PDIP which connects only
the logic core and the embedded program/
data memories.
PWRVDD
Supply voltage for the 42-PDIP which connects only
the I/O Pad Drivers. The application board must
connect both VDD and PWRVDD to the board
supply voltage.
PWRGND
Ground for the 42-PDIP which connects only the I/O
Pad Drivers. PWRGND and GND are
weakly connected through the common silicon
substrate, but not through any metal links. The
application board must connect both GND and
PWRGND to the board ground.
Port 0
Port 0 is an 8-bit open drain bi-directional I/O port.
As an output port, each pin can sink six TTL
inputs. When 1s are written to port 0 pins, the pins
can be used as high-impedance inputs.
Port 0 can also be configured to be the multiplexed
low-order address/data bus during accesses
to external program and data memory. In this mode,
P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash
programming and outputs the code bytes during
program verification. External pull-ups are
required during program verification.
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal
pull-ups. The Port 1 output buffers can
sink/source six TTL inputs. When 1s are written to
Port 1 pins, they are pulled high by the weak
internal pull-ups and can be used as inputs. As
inputs, Port 1 pins that are externally being
pulled low will source current (IIL,150 μA typical)
because of the weak internal pull-ups.
Some Port 1 pins provide additional functions. P1.0
and P1.1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and
the timer/counter 2 trigger input (P1.1/T2EX),
respectively. Furthermore, P1.4, P1.5, P1.6, and
P1.7 can be configured as the SPI slave port
select, data input/output and shift clock input/output
pins as shown in the following table.