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1. ABSTRACT
Energy Box is a device that calculates the cost of electricity consumed by a home, business, or electrically powered device. In this project our Box made of current transformer, IR sensor and magnetic reed switch. According to the energy Box calculates the reading with the help of the current transformer. IR sensor and magnetic reed switch are used to detect the theft in energy Box.
THEFT CONTROL SYSTEM
The theft in energy Box is the major drawback in our country because of theft more than lakes of money loss per state in our country. So our project deals about the theft control in energy Box by using embedded systems. To control the theft we use two types of theft controlling process namely tapering of seal in energy Box, underground power theft control .The first process of theft control by using IR (infrared) sensor. IR sensor is fixed in the energy Box screw with 12v rechargeable battery for identifying the tapering of seal. After identifying the theft IR sensor send the data to the micro controller and then message send to the government office by using RF. The second process of theft control by using the step down circuit fixed between 50 Box gap to analyze the underground theft. If the intruder cuts the underground cable at the time of a power cut the connection of sensors also disconnected. Then the data transfer also disconnected between the circuit and send the information about the disconnection between the circuit to the micro controller and then message send to the higher officer of the EB (electricity board).
BLOCK DIAGRAM DESCRIPTION
POWER SUPPLY
As we all know any invention of latest technology cannot b activated without source of power so it this fast moving world we deliberately need a proper power source which will be apt for particular requirement. The power supply section important one for circuit operation. It provides requirement power supply for every one blocks and it produce constant DC voltage.
MICROCONTROLLER (89S52)
It is the collection two timer/counter and have 2Kbytes of reprogrammable flash memory (10,000 write and erase cycles). These Register add memory location can be made to operate using the Software instruction that are incorporate as part of design. The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with2K bytes of Flash programmable and erasable read-only memory (PEROM).The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C2051 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.
OPERATIONAL AMPLIFIERS (LM324)
LM324 is a 14pin IC consisting of four independent operational amplifiers (op-amps) compensated in a single package. Op-amps are high gain electronic voltage amplifier with differential input and, usually, a single-ended output. The output voltage is many times higher than the voltage difference between input terminals of an op-amp.These op-amps are operated by a single power supply LM324 and need for a dual supply is eliminated. They can be used as amplifiers, comparators, oscillators, rectifiers etc. The conventional op-amp applications can be more easily implemented with LM324.
LED
It is indicated by using the LED. It is 1.2 V DC operated LED.
TRANSMITTER SECTION:
Transmitter section having Power supply and RF transmitter. The signals are produced by the sensor unit is encoded by Encoder IC HT 12E. RF Transmitter gives a RF output, which will be transmitted by the antenna in the free space.
RECEIVER SECTION:
Receiver section having RF Receiver, Decoder, Microcontroller, The Transmitted RF Signals are absorbed by the receiving antenna, and the RF signals are decoded by the Decoder IC HT 12D Chip.
CRYSTAL OSCILLATOR
The XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.
BUZZER
A buzzer or beeper is an audio signaling device, it is an electromechanical. Typical uses of buzzers and beepers include alarm and timer confirmation of users input such as a mouse click or keystroke. The function of buzzer is the, if any variations occurs in the circuit it horns the beep sound.
IR SENSOR
The correct positioning of the sender LED, the receiver LED with regard to each other and to the Op-Amp can also increase the performance of the sensor. First, we need to adjust the position of the sender LED with respect to the receiver LED, in such a way they are as near as possible to each others , while preventing any IR light to be picked up by the receiver LED before it hit and object and returns back. The easiest way to do that is to put the sender(s) LED(s) from one side of the PCB,
CIRCUIT DIAGRAM DESCRIPTION
The regulated 5V is used to power the Microcontroller.LM324, IR sensors, LCD, RF Module, LED1 indicates presence of power supply.
The 230V, 50MHz AC mains is stepped down by transformer X1 to deliver a secondary output of 12V, 500mA. The transformer output is rectified by full-wave rectifier module BR1, filtered by capacitor C6 and regulated by IC7805 (IC11). Capacitor C7 by passes the ripples present in regulated supply.
Assemble the circuit on a PCB to save time and minimize assembly errors. Carefully assemble the components and double click for any overlooked error. Use proper IC based for IC1,IC2 being an SMD chip ,it needs to be soldered at the side of PCB.
The program is written in C Language and compiled using Hi-Tech compiler along with MPLAB to generate hex code. The generated hex code is burnt into the microcontroller using a suitable programmer with configuration bit setting. The program is well commented and easy to understand.
The software for the microcontroller based parking system is written in ‘C’ Language and compiled using Keil μ Vision4 compiler. The generated hexcode is burnt into the microcontroller using a suitable programmer.
Micro controller AT89S52 (IC1) is at the heart of the system. It is an 8 bit microcontroller with 4kB of Flash programmable and erasable memory(PEROM), 128 bytes of RAM, 32 input/output (I/O) lines, two 16 bit timers/counters, a five-vector two level interrupt architecture, a full – duplex serial port, on-chip oscillator and clock circuitry.
Power-on reset for the microcontroller is provided by the combination of resistor R2 and capacitor C3. Switch S1q is used for manual reset. A11.0592 MHz crystal along with two 22pF capacitors provides the basic clock frequency to microcontroller AT89C51.
Microcontroller AT89C51 is at the heart of the circuit. It is an 8 bit microcontroller with 4kB of Flash programmable and erasable read only memory (PEROM). 128 bytes of RAM , 32 input/output(I/O) lines, two 16-bit timers/ counters, a five- vector two-level interrupt architecture, a full-duplex serial port, on-chip oscillator and clock circuitry.
Port 1,2 and 3 of the microcontroller are 8 bit bidirectional I/O port. Therefore port 0 is pulled up by resistor network RNW1. Port pins P0.0 through P0.7 of the microcontroller are connected to input pins 1 through 8 of IC2, respectively, without pull-up resistors.
LM 324 is low cost, single chip solution for electrical measurement. In operation, the chip interfaces with a shunt resistor (used as sensor). The sensor is connected to positive end of the LM324. IC LM324 has a circuit and a fixed function for calculation of the output value from the sensor. The power supply for this IC is derived directly from mains using the capacitor divider network comprising of capacitors C3,C4. The regulated 5v is fed to IC1.
Two IR sensor pairs (31,33) are used for transmitting and receiving signals The receiver circuit consists of the following components: 1. Resistors. 2. IR LED. The receiver unit consists of a sensor and its associated circuitry. In receiver section, the first part is a sensor, which detects IR pulses transmitted by IR-LED. Whenever a train crosses the sensor, the output of IR sensor momentarily transits through a low state. As a result the monostable is triggered and a short pulse is applied to the port pin of the 8051 microcontroller. On receiving a pulse from the sensor circuit, the controller activates the circuitry required for closing and opening of the gates and for track switching. The IR receiver circuit is shown in the figure below.
We are going to use Infra Red transmitters and Receivers for each parking slot. The IR Receivers are connected to Microcontroller. IR rays are obstructed when a car is parked in any parking slot. Thus Controller will come to know that which slot is empty and which slot is full We have chosen IR module instead of RF module because we want a receiver having line of sight communication with the transmitter. But RF does not require line of sight communication. And in case of IR, there is scope for false triggering due to sunlight or headlight of car. So considering all these points we have finalized to use IR module.
HT12E and HT12D are CMOS ICs with a working voltage range of 2.4V to 12V. Encoder HT12E has eight address lines and four address/ data lines. The data set on these twelve lines (address and address/ data lines) is serially transmitted when transmit-enable TE pin (pin 14) is low. The data output appears serially on DOUT pin. Data is transmitted four times in succession.
The frequency of the pulses of data transmission may lie between 1.5 kHz and 7 kHz depending on the resistor value used between oscillator pins 15 and 16. The internal oscillator frequency of decoder HT12D is 50 times the oscillator frequency of encoder HT12E. The values of timing resistors connected between pins 15 and 16 of Ht12E and HT12D, for the given supply voltages, can be determined from the graphs given in the datasheet of the respective chips. The resistor values used in the circuit here are chosen for approximately 3kHz frequency for encoder HT12E and 150 kHz for decoder HT12D at a VDD of 5V. Decoder HT12D receives data from HT12E on its DIN pin serially. If the transmitted address matches the address of the decoder four times in succession, valid transmission pin (VT) through AD11 of the HT12E appears on pins D8 through D11 of the Ht12D.
Port 1,2 and 3 of the microcontroller are 8 bit bidirectional I/O port. Therefore port 0 is pulled up by resistor network RNW1. Port pins P0.0 through P0.7 of the microcontroller are connected to input pins 1 through 8 of IC2, respectively, without pull-up resistors.
FEATURES
• Compatible with MCS-52 Products
• 8K Bytes of In-System Programmable (ISP) Flash Memory
• 4.0V to 5.5V Operating Range
• Fully Static Operation: 0 Hz to 33 MHz
• Three-level Program Memory Lock
• 256 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-bit Timer/Counters
• Eight Interrupt Sources
• Full Duplex UART Serial Channel
• Low-power Idle and Power-down Modes
• Interrupt Recovery from Power-down Mode
• Watchdog Timer
• Dual Data Pointer
• Power-off Flag
DESCRIPTION
The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinot. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.
The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.
PIN DESCRIPTION
VCC Supply voltage.
GND Ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI); Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table. Port 3 also receives some control signals for Flash programming and verification.
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.
ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle,except two PSEN activations are skipped during each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external pro-gram memory locations starting at 0000H up to FFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable volt-age (VPP) during Flash programming
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) .Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.
Timer 2 Registers:
Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H, RCAP2L) is the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.
INTERRUPT REGISTERS:
The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.
Dual Data Pointer Registers:
To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.
MEMORY ORGANIZATION
MCS-51 devices have a separate address space for Pro-gram and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.
Program Memory
If the EA pin is connected to GND, all program fetches are directed to external memory.
On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFH are to external memory.
Data Memory
The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.
When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access of the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
MOV @R0, #data
WATCHDOG TIMER
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 13-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT over-flow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.
Using the WDT
To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT over-flow. The 13-bit counter overflows when it reaches 8191 (1FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 8191 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.
WDT during Power-down and Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode.
Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.
UART
The UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52. For further information on the UART operation, refer to the ATMEL Web site (http://www.atmel.com). From the home page, select ‘Prod-cuts’, then ‘8051-Architecture Flash Microcontroller’, then ‘Product Overview’.
Timer 0 and 1
Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’ operation, refer to the ATMEL Web site (http://www.atmel.com). From the home page, select ‘Products’, then ‘8051-Architecture Flash Microcontroller’, then ‘Product Overview’.
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.
Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON.
This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure 5.
Auto-reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.
Baud Rate Generator
Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode.
The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the following equation.
The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency).
Timer 2 as a baud rate generator is shown in Figure 8. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt.
INTERRUPTS
The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software.The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 11. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 12. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maxi-mum voltage high and low time specifications must be observed.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.
When idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.
Power-down Mode
In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held
PROGRAMMING THE FLASH
Parallel Mode
The AT89S52 is shipped with the on-chip Flash memory array ready to be programmed. The programming interface needs a high-voltage (12-volt) program enable signal and is compatible with conventional third-party Flash or EPROM programmers.
Programming Algorithm:
Before programming the AT89S52, the address, data, and control signals should be set up according to the Flash programming mode table and Figures 13 and 14. To program the AT89S52, take the following steps:
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V.
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 50 µs.
Data Polling:
The AT89S52 features Data Polling to indicate the end of a byte write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written data on P0.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.
Ready/Busy:
The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0 is pulled high again when programming is done to indicate READY.
Program Verify:
If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The status of the individual lock bits can be verified directly by reading them back.
Chip Erase:
In the parallel programming mode, a chip erase operation is initiated by using the proper combination of control signals and by pulsing ALE/PROG low for duration of 200 ns - 500 ns.
In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase instruction. In this mode, chip erase is self-timed and takes about 500 ms. During chip erase, a serial read from any address location will return 00H at the data output.
PROGRAMMING THE FLASH
Serial Mode
The Code memory array can be programmed using the serial ISP interface while RST is pulled to VCC. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RST is set high, the Programming Enable instruction needs to be executed first before other operations can be executed. Before a reprogramming sequence can occur, a Chip Erase operation is required.
The Chip Erase operation turns the content of every memory location in the Code array into FFH. Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than 1/16 of the crystal frequency. With a 33 MHz oscillator clock, the maximum SCK frequency is 2 MHz