25-08-2017, 09:32 PM
Microprocessor System Design Programmable Interrupt Controller
Microprocessor System Design.ppt (Size: 758 KB / Downloads: 42)
Answering an Interrupt
Save status
FR, IP, CS
Service the interrupt
Interrupt service routing (ISR) or Interrupt handler
Based on Interrupt vector number
From Interrupt vector table
Four bytes for every interrupt: CS:IP
Return to original position by IRET
Difference with Call
CALL FAR can jump to any location (1M range)
Hardware interrupts can come at any time.
Interrupts are maskable.
After CALL only CS:IP is saved
End of routine: RETF vs. IRET.
Interrupt Categories
Hardware interrupts:
Only 3 pin, but how 256 interrupt?
INTR (in), NMI (in), and INTA (out)
INTR can be masked by CLI / STI
Active high.
80x86 finished instruction.
Push FR, CS, IP
NMI: INT 02.
Software interrupts
INT nn
Example: INT 21H (DOS functions)
Predefined Interrupts
INT 00 (divide error)
INT 01 (single step)
Set Trap flag (how?)
PUSHF, POP AX, …
Trace in debug
INT 02 (NMI)
INT 03 (breakpoint)
INT 04 (signed number overflow)
INT) instruction
Examine Interrupt vector table.
Examine INT 12H (size of conventional RAM in AX)
Edge Triggered and Interrupt Sharing
Level triggered mode: IRQ line should be brought down before EOI.
Edge triggered mode: noise on IRQ lines might cause false interrupts.
New computer and busses.
Level triggered.
Interrupt sharing.