05-11-2012, 06:03 PM
An Introduction to SystemVerilog
SystemVerilog_veriflcation.ppt (Size: 159 KB / Downloads: 69)
What is SystemVerilog?
SystemVerilog is a hardware description and Verification language(HDVL)
SystemVerilog is an extensive set of enhancements to IEEE 1364 Verilog-2001 standards
It has features inherited from Verilog HDL,VHDL,C,C++
Adds extended features to verilog
System verilog is the superset of verilog
It supports all features of verilog plus add on features
It’s a super verilog
additional features of system verilog will be discussed
System Verilog Concepts
No begin end required
Return can be used in task
Function return values can have a “void return type”
Functions can have any number of inputs,outputs and inouts including none
What is OOP?
OOP breaks a testbench into blocks that work together to accomplish the verification goal
Why OOP
Highly abstract system level modelling
Classes are intended for verification
Classes are easily reused and extended
Data security
Classes are dynamic in nature
Easy debugging, one class at a time
Assertion
Used primarily to validate the behaviour of a design
An assertion is a statement about a designs intended behaviour
In-line assertions are best added by design engineers
Interface assertions are best added by verification engineers
An assertion’s sole purpose is to ensure consistency between the designer’s intention and design implementation
It increases the bug detection possibility during RTL design phase