27-09-2014, 11:24 AM
FPGA Implementation of high speed 8-bit Vedic
multiplier using barrel shifter
FPGA Implementation.pdf (Size: 1.31 MB / Downloads: 30)
Abstract-
This paper describes the implementation of an 8-bit
Vedic multiplier enhanced in terms of propagation delay when
compared with conventional multiplier like array multiplier,
Braun multiplier, modified booth multiplier and Wallace tree
multiplier. In our design we have utilized 8-bit barrel shifter
which requires only one clock cycle for ‘n’ number of shifts. The
design is implemented and verified using FPGA and ISE
Simulator. The core was implemented on Xilinx Spartan-6 family
xc6s1x75T-3-fgg676 FPGA. The propagation delay comparison
was extracted from the synthesis report and static timing report
as well. The design could achieve propagation delay of 6.781ns
using barrel shifter in base selection module and multiplier.
INTRODUCTION
Arithmetic operations such as addition, subtraction and
multiplication are deployed in various digital circuits to speed
up the process of computation. Arithmetic logic unit is also
implemented in various processor architectures like RISC [2],
CISC etc., In general, arithmetic operations are performed
using the packed-decimal format. This means that the fields
are first converted to packed-decimal format prior to
performing the arithmetic operation, and then converted back
to their specified format (if necessary) prior to placing the
result in the result field.
Vedic mathematics has proved to be the most robust
technique for arithmetic operations. In contrast, conventional
techniques for multiplication provide significant amount of
delay in hardware implementation of n-bit multiplier.
Moreover, the combinational delay of the design degrades the
performance of the multiplier. Hardware-based multiplication
mainly depends upon architecture selection in FPGA or ASIC.
In this work we have put into effect a high speed
Vedic multiplier using barrel shifter. The sutra was
implemented by modified design of “Nikhilam Sutra” [1] due
to its feature of reducing the number of partial products. The
barrel shifter used at different levels of design drastically
reduces the delay when compared to conventional multipliers.
The hardware implementation of Vedic multiplier
using barrel shifter contributes to adequate improvement of
the speed in order to achieve high outturn.
VEDIC SUTRAS
Vedic Sutras apply to and cover almost every branch
of Mathematics. They apply even to complex problems
involving a large number of mathematical operations.
Application of the Sutras saves a lot of time and effort in
solving the problems, compared to the formal methods
presently in vogue. Though the solutions appear like magic,
the application of the Sutras is perfectly logical and rational.
The computation made on the computers follows, in a way,
the principles underlying the Sutras. The Sutras provide not
only methods of calculation, but also ways of thinking for
their application.
Application of the Sutras improves the computational
skills of the learners in a wide area of problems, ensuring both
speed and accuracy, strictly based on rational and logical
reasoning. Application of the Sutras to specific problems
involves rational thinking, which, in the process, helps
improve intuition that is the bottom - line of the mastery of the
mathematical geniuses of the past and the present such as
Aryabhatta, Bhaskaracharya, Srinivasa Ramanujan, etc.,
.CONCLUSION.
In our design, efforts have been made to reduce the
propagation delay and achieved an improvement in the
reduction of delay with 45% when compared to array
multiplier, booth multiplier and conventional Vedic multiplier
implementation on FPGA [4]. The high speed implementation
of such a multiplier has wide range of applications in image
processing, arithmetic logic unit and VLSI signal processing
a.
The future scope of this particular work can be extended in
design of ALU’s in RISC processor.