21-08-2012, 12:57 PM
Morse Code Generator Using FPGA
Morse Code.docx (Size: 5.43 MB / Downloads: 194)
Abstract
This paper presents a system which can automatically code and decode the Morse Code using FPGA. The purposed of this project is to build a generator to generate Morse code for Police Training Centre to ensure their understanding of Morse code is the same as the project do. The output of DIT (short pulse) and DAH (long pulse) representation of Morse code and display the desired output in on the Seven-Segment after the input had been process by the FPGA.
INTRODUCTION
Morse code is a method of sending text messages by keying in a series of electronic pulses. It can be transmitted using on-off tones, lights, or clicks that can be directly understood by skilled listener or observer without special equipment, as sometimes happens between ships at sea. It is used in emergencies to transmit distress signals when no other form of communication is available. In this project, Morse code is used to test the accuracy of the Morse code learning tool in the police training center. The Morse code will be performing as light and sound using a speaker. There are two types of pulse these are a short pulse known as a “dot” and a long pulse known as a “dash”.
Early work done with Morse code used telegraphs to send transmissions incorporating the “dot” and the “dash” to formulate characters. This implemented system will take the basic concepts and advance them further to form a generator. That can visually display the intended ASCII input and produce sounds and light associated with Morse code at the same instance. Then, the code in the form of Morse code will be automatically translated to the form of letters or numbers.
Programming software (Verilog)
The Altera Quartus II is a software tool produced by Altera for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.
This software package will be use in to build the project and provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II are includes solution for all phases of FPGA design.
Verilog hardware description language is one of the programming software used to model electronic systems. There are two assignment operators, a blocking assignment (=), and a non-blocking (<=) assignment. The non-blocking assignment allows designers to describe a state-machine update without needing to declare and use temporary storage variables.
Verilog modules that conform to a synthesizable coding style is known as RTL (register-transfer level) which can be physically realized by synthesis software. Synthesis software algorithmically transforms the Verilog abstract source into a netlist, a logically equivalent description consisting only of elementary logic primitives (AND, OR, NOT, flip-flops, etc.).
Altera DE2 Development and Education Board
FPGAs are digital integrated circuit (ICs) that contain configurable (programmable) blocks of logic along with configurable interconnects between the blocks and will be the heart of all the circuits. Depending how they are implemented, some FPGAs may only be programmed a single time, while others may be reprogrammed over and over again [4].
The Altera DE2 development and education board is the vehicle used to implement this project. The DE2 board is designed to support a wide range of experiments. It combines a variety of logic and I/O devices onto single printed-circuit board and allows configuring and controlling these devices to create different applications. The I/O devices on the DE2 are a small LCD display, numerous LEDS (lights), and switches. In addition, the DE2 has connections to a variety of external I/O devices such as PS2 keyboard. The FPGA connects to all logic and I/O devices on the DE2.