31-05-2012, 02:00 PM
Multi-Clock SoC Design using Protocol Conversion
Multi-Clock SoC Design using Protocol Conversion.pdf (Size: 654.6 KB / Downloads: 34)
Abstract
The automated design of SoCs from pre-selected IPs that
may require different clocks is challenging because of the
following issues. Firstly, protocol mismatches between IPs
need to be resolved automatically before IPs are integrated.
Secondly, the presence of multiple clocks makes the protocol
conversion even more difficult. Thirdly, it is desirable that
the resulting integration is correct-by-construction, i.e., the
resulting SoC satisfies given system-level specifications. All
of these issues have been studied extensively, although not
in a unifying manner. In this paper we propose a framework
based on protocol conversion that addresses all these
issues.
Introduction
A system-on-a-chip (SoC) consists of multiple components
(IPs) that collaborate and communicate with each
other to achieve system behaviour. The SoC design process
is affected by several issues like the selection of IPs, their
interconnection into overall system, and validation of correctness
of the overall system. The main problems with the
integration of preselected IPs are, (a) the possibility of control,
data or clock mismatches [9] between IP protocols that
prevent proper inter-IP communication, and, (b) the problem
of ensuring that IPs (after mismatches are resolved) integrate
such that desired high-level behaviour is met.
RelatedWork
A number of protocol conversion approaches for SoC
have been proposed earlier [2, 5, 9]. In [5], a correct-byconstruction
SoC design technique is presented. The work
identifies precise conditions under which two IPs are compatible,
and an automatic algorithm is used to generate an
interface to make them compatible. A protocol conversion
approach based on [5] is presented in [2]. The main contributions
of this approach are the precise modelling of commercial
bus protocols, a protocol conversion algorithm that
always yields converters that can be translated to HDL, and
converter sizes that are bounded by the size of the given
protocols. However, this approach generates converters for
protocol pairs only and bridges data-width mismatches on
an abstract level by avoiding unbounded data operations on
any path in the converted system.
Converters
A converter acts as an interface between IPs and their
environment (other IPs). It controls the participating protocols
at each clock tick (of the base clock of the given clock
automaton) by following a precise sequence of interactions
with the environment and the protocols (shown in Fig. 3).
Conclusions
This paper proposes a unifying framework for the design
of SoCs in which control, data-width and clock mismatches
between multiple IPs can be resolved, and those
IPs can be integrated into a correct-by-construction SoC.
This is unlike existing approaches that focus exclusively on
mismatch resolution or correct-by-construction design. In
the proposed setting, IP protocols are described using Synchronous
Kripke Structures, each executing using its individual
clock. An automatic converter generation algorithm
based on tableau construction is used to generate a converter,
if possible, that bridges mismatches and guides the
IPs such that their interaction is consistent with high-level
control .