14-09-2013, 02:40 PM
Multipliers
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Expensive and slow operations
Multiplication units in state of the art DSP and P
Complex adders – earlier discussion on adders relevant
Partial products; accumulation; final summation
Partial Product Generation
Logical AND of multiplicand X and multiplier bit Yi
Adding zeros has no impact on results
Can reduce no. or partial products by half!!
Eg. 0111 1110 ≡ 1000 0010 where 1 = -1
So only two partial products need be added!
Leads to less additions with area reduction and higher speed
Alternating 10101010 for eight bit is the worst case!
Multiplying with {-2,-1, 0, 1, 2} versus {1, 0}; needs encoding
Used modified Booth’s recoding for consistent operation size
The Barrel Shifter
# rows = # data word length
Control wire routed diagonally
Signal goes through only one transmission gate (theoretically delay is constant for shift value and shifter size)
Reality – delay depends on shift widths due to parasitic capacitance
Layout and area dominated by wiring and not active elements
Need decoder to interpret shift data to route signal to appropriate wire