21-01-2013, 04:18 PM
3D IC technology
3D IC technology.ppt (Size: 626.5 KB / Downloads: 60)
Motivation
Interconnect structures increasingly consume more of the power and delay budgets in modern design
Plausible solution: increase the number of “nearest neighbors” seen by each transistor by using 3D IC design
Smaller wire cross-sections, smaller wire pitch and longer lines to traverse larger chips increase RC delay.
RC delay is increasingly becoming the dominant factor
At 250 nm Cu was introduced alleviate the adverse effect of increasing interconnect delay.
130 nm technology node, substantial interconnect delays will result.
Performance Characteristics
Timing
Energy
With shorter interconnects in 3D ICs, both switching energy and cycle time are expected to be reduced
Timing
In current technologies, timing is interconnect driven.
Reducing interconnect length in designs can dramatically reduce RC delays and increase chip performance
The graph below shows the results of a reduction in wire length due to 3D routing
Discussed more in detail later in the slides
Energy performance
Wire length reduction has an impact on the cycle time and the energy dissipation
Energy dissipation decreases with the number of layers used in the design
Following graphs are based on the 3D tool described later in the presentation
Design tools for 3D-IC design
Demand for EDA tools
As the technology matures, designers will want to exploit this design area
Current tool-chains
Mostly academic
We will discuss a tool from MIT
Intro to Global Routing
Overview
Global Routing involves generating a “loose” route for each net.
Assigns a list of routing regions to a net without actually specifying the geometrical layout of the wires.
Followed by detailed routing
Finds the actual geometrical shape of the net within the assigned routing regions.
Usually either sequential or hierarchical algorithms
Extending to 3D
Routing in 3D consists of routing a set of aligned congruent routing regions on adjacent wafers.
Wires can enter from any of the sides of the routing region in addition to its top and bottom
3D router must consider routing on each of the layers in addition to the placement of the inter-waver vias
Basis idea is: You connect a inter-waver via to the port you are trying to connect to, and route the wire to that via on the 2D plane.
All we need now is enough area in the 2D routing space to route to the appropriate via