17-08-2012, 12:12 PM
New Josephson-CMOS Interface Amplifier
CMOS Interface Amplifier.pdf (Size: 664.12 KB / Downloads: 24)
INTRODUCTION
JOSEPHSON superconductor digital logic employs signals
of about one millivolt, which permits very high speed logic
operations with very lowpower dissipation. It is necessary under
many circumstances to interface the superconductor logic to
semiconductor logic, which operates with signals of volt level.
Our particular interest is in an amplifier interface from superconductor
logic to CMOS circuits in a hybrid Josephson-CMOS
memory, but similar situations will be found in other systems. A
block diagram of the 4 K memory is shown in Fig. 1. The goal
is to operate at a few gigahertz with small delays and to dissipate
very low power. Millivolt-level signals from the processor
are amplified in two stages. The first stage is a Suzuki stack [1]
or similar Josephson driver producing an output of tens of millivolts
and the second stage is either a hybrid amplifier (as in
the Ghoshal amplifier [2]–[4]) or a CMOS amplifier as in the
present work (and in earlier work [5], [6]).
LATCH AMPLIFIER
the core of the CMOS latch amplifier. This circuit
comprises a carefully balanced flip-flop (cross-coupled inverters)
with ancillary circuits that ensure correct operation by
balancing the flip-flop during the reset phase.
The function of the circuit is to amplify an input of tens of
millivolts from the Josephson driver to CMOS volt levels.
CALIBRATION CIRCUIT
The threshold voltages of the amplifier transistors are expected
to have somewhat random values due to process and
material nonuniformities. This has the effect of introducing a
random offset voltage at the amplifier input, which may be comparable
to the amplitude of the signals that we are trying to detect.
Therefore, we have developed a self-calibration circuit to
compensate for this offset to increase the amplifier sensitivity
and provide an acceptable bit-error rate for our circuit.
Calibration is intended to be performed only once, when
power is initially applied to the system. Each amplifier has its
own calibration circuit, and calibration occurs in parallel for all
amplifiers.
SUMMARY
We have presented the design of a new CMOS amplifier with
its calibration circuit to be used as the second stage of an amplifier
system to raise the millivolt-level Josephson logic signal
voltages to CMOS volt levels. We explored the possible use
of stacked Suzuki stacks as the Josephson driver. We demonstratedwith 4 K CMOS.)We showed functionality results for the superstacks
and a precursor CMOS latch amplifier. We will continue
our study of the Suzuki stacks and superstacks to achieve wider
operating margins and we will fabricate complete amplifiers to
confirm the delay predictions of our simulations.