30-11-2012, 06:01 PM
Nonideal Transistors
Nonideal.ppt (Size: 578 KB / Downloads: 63)
Simulated nMOS I-V Plot
180 nm TSMC process
BSIM 3v3 SPICE models
What differs?
Less ON current
No square law
Current increases
in saturation
Channel Length Modulation
Reverse-biased p-n junctions form a depletion region
Region between n and p with no carriers
Width of depletion Ld region grows with reverse bias
Leff = L – Ld
Shorter Leff gives more current
Ids increases with Vds
Even in saturation
Body EffectVt:
gate voltage necessary to invert channel
Increases if source voltage increases because source is connected to the channel
Increase in Vt with Vs is called the body effect
Leakage Sources
Subthreshold conduction
Transistors can’t abruptly turn ON or OFF
Junction leakage
Reverse-biased PN junction diode current
Gate leakage
Tunneling through ultrathin gate dielectric
Subthreshold leakage is the biggest source in modern transistors
Process Corners
Process corners describe worst case variations
If a design works in all corners, it will probably work for any variation.
Describe corner with four letters (T, F, S)
nMOS speed
pMOS speed
Voltage
Temperature