26-09-2013, 01:10 PM
On Single-Electron Technology Full Adders
Single-Electron Technology .doc (Size: 1.74 MB / Downloads: 47)
Abstract
This paper reviews several full adder (FA) designs in single electron technology (SET). In addition to the structure and size (i.e. number of devices), this paper tries to provide a quantitative and qualitative comparison in terms of delay, sensitivity to (process) variations, and complexity of the design. This will allow for a better understanding of the advantages and disadvantages of each solution. An optimization of a SET FA (combining one of the SET FAs with a static buffer), together with a new SET FA design (based on capacitive SET threshold logic gates), will also be described and compared with the other SET FAs.
Introduction
The scaling of Complementary Metal Oxide Semiconductor (CMOS) transistors has so far provided lower cost and higher performance circuits. However, further progress of integration scale will be hindered by a variety of physical effects. The most important effects are the increase in power consumption and the decrease in reliability [1]–[4]. These problems have motivated an active search in quest for both short- and long-term solutions.
Types of Single-electron Technology Full Adders
The first two types of the SET FAs proposed are based on MAJ gates [19], [20], but differ in the way the MAJ gates are implemented. The third SET FA is based on pass-transistor logic (PTL) [21], and the fourth one is based on TLGs [22]. The fourth one will be modified by matching the TLG gate detailed in [22] with a static buffer, and optimizing the capacitor values. The new SET FA we present in this article is also TLG based [23]. The different types of SET FAs are described in the following subsections. The description will be accompanied by simulation results to verify the functionality of each SET FA. All the simulations were done using SIMON [26]. The input signals used in these simulations cover all the eight possible combinations of the inputs a, b, and ci, as shown in Fig. 2, where the voltage levels (0 mV and 6.5 mV) correspond to the SET FA introduced in [19].