04-09-2012, 05:02 PM
Binary-coded decimal digit multipliers
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Abstract:
With the growing popularity of decimal computer arithmetic in scientific, commercial,
financial and Internet-based applications, hardware realisation of decimal arithmetic algorithms is
gaining more importance. Hardware decimal arithmetic units now serve as an integral part of some
recently commercialised general purpose processors, where complex decimal arithmetic operations,
such as multiplication, have been realised by rather slow iterative hardware algorithms.
However, with the rapid advances in very large scale integration (VLSI) technology, semi- and
fully parallel hardware decimal multiplication units are expected to evolve soon. The dominant
representation for decimal digits is the binary-coded decimal (BCD) encoding. The BCD-digit
multiplier can serve as the key building block of a decimal multiplier, irrespective of the degree
of parallelism. A BCD-digit multiplier produces a two-BCD digit product from two input BCD
digits. We provide a novel design for the latter, showing some advantages in BCD multiplier
implementations.
Introduction
Decimal computer arithmetic is preferred in decimal data
processing environments such as scientific, commercial,
financial and Internet-based applications [1]. Ever
growing needs for processing power, required by applications
with intensive decimal arithmetic, cannot be met
by conventional slow software simulated decimal arithmetic
units [1]. However, their hardware counterparts as an
integral part of recently commercialised general purpose
processors [2] are gaining importance. Binary-coded
decimal (BCD) encoding of decimal digits has conventionally
dominated decimal arithmetic algorithms, whether
realised by hardware or in software.
General BCD multiplication
A general conventional paper and pencil view of decimal
multiplication is depicted in Fig. 1, where in this figure
and throughout the paper uppercase (lowercase) letters are
used for decimal (binary) digits.
l such that the former weighs ten times as much as
the latter; hence, h (for high) and l (for low) superscripts.
Using BCD encoding for all decimal digits of Fig. 1 leads
to a general BCD multiplication scheme, for which a hardware
implementation may be achieved by one of the following
sequential, semi- or fully parallel approaches.
Comparison with previous works
We have not encountered any direct implementation for
BCD digit multipliers in the literature, except for look-up
table implementations (e.g. [6, 7]). The latest work based
on decimal digit-by-digit multiplier converts the BCD operands
to signed digits in [25, 5] and uses a
signed-digit-by-signed-digit multiplier on a word-by-digit
basis to generate the partial products, also represented by
signed digits [4]. The latter work does not provide any
area and time measures that can be used as a comparison
basis.
To compare our results with other published works, we
have designed iterative BCD multipliers based on the
delay-optimised and area-optimised BCD-digit multipliers
of the previous section. One hardware realisation of BCD
multipliers [3] uses the iterative approach with precomputed
easy multiples as explained in Section 2. Our approach for
partial product generation is different from that of [3], but
both designs use the same method for partial product
accumulation. Therefore for the sake of accurate comparison,
we deemed it enough to run simulations only on the
first part of multipliers, and measured areas of the partial
product generation logic for the two approaches through
simulation based on a 0.25 mm Complementary metal
oxide semiconductor (CMOS) standard process.
Conclusion
We have designed a novel BCD-digit multiplier cell that
can be used in conventional iterative BCD multiplier circuits.
We showed that this design alternative leads to 30%
savings in the area of partial product generation logic. It
does neither affect the rest of the multiplier circuitry, nor
does it add to the overall delay of a pipelined implementation.
Our design leads to more regular VLSI implementation,
and does not require special registers for storing
easy multiples. Further research is on going on efficient
use of the designed BCD-digit multiplier in semi- and
fully parallel BCD multipliers.