28-03-2012, 04:19 PM
Microarchitecture
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Specifications
Load-store/Reg-Reg/Nonpipelined architecture
23 instructions
6 arithmetic + 8 logical + 4 datapath + 5 branch
4-stage instruction execution – IF, ID, EX, ST
Harvard memory architecture
8-bit data & address bus
Two 8-bit memory mapped I/O registers
One special purpose status register
13-general purpose CPU registers
Uniform instruction width for all the instructions