22-09-2012, 01:42 PM
An Innovative Digital Control Architecture for Low-Voltage, High-Current DC–DC Converters With Tight Voltage Regulation
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Abstract
This paper describes an innovative digital control
architecture for low-voltage, high-current dc–dc converters, based
on a combination of current-programmed control and variable
frequency operation. The key feature of the proposed architecture
is the low complexity: only two digital-to-analog converters (DACs)
with low resolution (7-b) are used for control. An original control
algorithm is used to reduce quantization effects to negligible
levels, in spite of the low resolution of the DACs. Thanks to this
algorithm, both static and dynamic output voltage regulation are
improved with respect to traditional digital solutions. Adaptive
voltage positioning and active current sharing are inherently
provided by the new architecture. A detailed description of the
control strategy is given with reference to a single-phase buck
converter. Extension to multiphase converters is straightforward.
The digital control architecture is experimentally verified on a
FPGA-based four-phase prototype buck converter operating at
350 kHz/phase. Output voltage tolerance within 0 5% is experimentally
demonstrated, along with negligible quantization effects
and fast transient response. The features and the performance of
the proposed architecture make it a valuable candidate for the
control of next generation voltage regulator modules.
INTRODUCTION
RECENTLY, there has been a growing interest in digital
controllers for high-frequency, low-to-medium power
dc-dc converters, due to their low power consumption, immunity
to noise and analog component variations, ease of
integration with other digital systems, ability to implement
sophisticated control schemes [1]–[11]. Among the various
advantages of digital approach, design flexibility is the most
valuable one. The control algorithm is described at the functional
level using a hardware description language [very
high speed integrated circuit hardware description language
(VHDL)]. Sophisticated simulation, synthesis and verification
tools are available for translating the VHDL design into
standard-cell application specific integrated circuits (ASICs)
or field programmable gate arrays (FPGAs). The design can
be easily adapted to different technologies or modified to meet
a different application or a new set of specifications, thus
providing very fast time-to-market.
Slope Compensation
It is well known that peak current mode control may lead
to subharmonic oscillation if . This is not an issue
in low-voltage, high-current converters, since the bus voltage
is quickly moving from 5 V to 12 V or even 48 V due to the
quest for better system efficiency. Nevertheless, in some applications
conversion from 5 V to 3.3 V or 2.5 V is still required. In
these cases, the slope compensation technique [15] can be used
to ensure converter stability. In practice, an artificial ramp has
to be subtracted to the peak reference value . In the proposed
controller, this ramp can be easily generated digitally by decrementing
the DACI input code at the clock frequency. As soon
as the peak inductor current reaches the value set by DACI the
ramp is reset.
Multi-Phase Topology
A digitally controlled multiphase converter can be simply derived
from the single-phase converter described above, by resorting
to a master-slave architecture. Each slave (phase) is a
buck converter that receives two signals from the master controller:
a peak current level signal and a turn-on signal. The slave
is operated in peak-current mode: it turns off when the inductor
current reaches the fixed peak value and it turns on when
it receives the corresponding signal from the master controller.
The master controller senses the output voltage level and activates
one phase each time the error voltage intercepts the
DACV output voltage. A suitable algorithm must be devised for
selecting which phase has to be turned on at this specified time.
The simplest algorithm for phase activation is based on a circular
selection scheme, that is, phases are cyclically turned on.
Fig. 8 shows a block diagram of a three-phase master-slave configuration
based on this algorithm. The master block includes
the digital controller, the D/A converters (DACI andDACV) and
a DEMUX that is cyclically scanned for distributing the turn-on
signals. If the are N slaves, each slave works at a switching frequency
of , where is the frequency of the voltage ramp
produced by DACV. This architecture is very flexible. An arbitrary
number of slave units can be added just by increasing the
number of DEMUX outputs.
CONCLUSION
This paper describes a new digital controller for low-voltage,
high-current dc–dc switching converters with tight requirements
on output voltage regulation. The main features of the controller
are:
i) fully reconfigurable digital architecture, with adaptive
voltage positioning and active current sharing capabilities;
ii) reduced complexity, due to the use of low-resolution
(7-b) DACs;
iii) negligible quantization effects, thanks to an original control
algorithm which exploits current programming and
variable frequency operation.
It must be pointed out that a traditional digital controller
having the same performance would have required a 10-b
DPWM and a 9 equivalent bit ADC [6]. Both these circuital
blocks are by far more complex and critical and require more
space than a 7-b DAC. The proposed architecture is thus
suitable for high-volume, low-cost integrated dc–dc controllers.