24-07-2012, 04:15 PM
Optimization of area for a VLSI Architecture at the FLOOR PLAN LEVEL
VLSI Architecture.pptx (Size: 1,017.34 KB / Downloads: 36)
INTRODUCTION
WHY ARE WE INTRESTED IN AREA OPTIMIZATION?
Cost of VLSI chip depends on several factors:-
Wire Length
What is FLOORPLANNING?
In electronic design automation , a floorplan of an integrated circuit is a schematic representation of tentative placement of its major functional blocks.
In modern electronic design process floorplans are created during the floorplanning design stage, an early stage in the hierarchical approach to chip design.
Depending on the design methodology being followed, the actual definition of a floorplan may differ.
METHODOLOGY
A String of symbols obtained by traversing a binary tree in post order.
Rules for Polish Expression:
Number of operand is n then the number of operator should be n-
Let k=number of elements in 1st operand chain then the number of elements in the 1st operator chain must be equals to k-1.
If k is the number of elements in the last operand chain then the number of elements in the last operator chain may be k or k+1.