10-09-2016, 11:18 AM
1454345041-ALU.docx (Size: 12.17 KB / Downloads: 9)
Abstract:
In this paper, a 4-bit arithmetic logic unit (ALU) is implemented which contains 2:1 multiplexer , 4:1 multiplexer and full adder that performs both arithmetic calculations such as Additions, subtractions etc., and logical calculations such as And, Or etc. In this paper ALU is implemented using the technique of power GDI that uses GDI cells for implementing multiplexers and full adder. Using GDI cells reduces the number of transistors required in designing of multiplexers and full adder. The simulation is done in software named Tanner EDA 13.0 that uses TSMC BSIM 250nm technologies. The simulation results shows that this technique consumes reduced power occupying less surface area with high speed than that of existing systems like CMOS and pass transistor logic techniques.
Keywords used: GDI, ALU, pas transistor logic.
Introduction:
In the fast growing technology, scaling of devices should be minimized. The same should be applied to ALU. The challenge in front of us is to design an ALU that is applicable to high speed low power microprocessors and microcontrollers. In past many methodologies are developed by many people like CMOS, BICMOS, etc. This paper utilizes the concept of Power GDI technique for designing adder, multiplexers that occupies very low space.
This paper deals with the previous works, description of power GDI technique, ALU design and its schematic, simulation results and finally conclusion.