18-10-2012, 05:37 PM
Organization of Intel 8086 Microprocessor
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General Data Registers:
The registers AX, BX,CX and DX are the general purpose 16-bit registers.
AX is used as 16-bit accumulator. The lower 8-bit is designated as AL and higher 8-bit is designated as AH. AL can be used as an 8-bit accumulator for 8-bit operation.
All data register can be used as either 16 bit or 8 bit. BX is a 16 bit register, but BL indicates the lower 8-bit of BX and BH indicates the higher 8-bit of BX.
The register CX is used default counter in case of string and loop instructions.
The register BX is used as offset storage for forming physical address in case of certain addressing modes.
DX register is a general purpose register which may be used as an implicit operand or destination in case of a few instructions.
Segment Registers:
The 8086 architecture uses the concept of segmented memory. 8086 able to address to address a memory capacity of 1 megabyte and it is byte organized. This 1 megabyte memory is divided into 16 logical segments. Each segment contains 64 kbytes of memory.
There are four segment register in 8086
• Code segment register (CS)
• Data segment register (DS)
• Extra segment register (ES)
• Stack segment register (SS)
Code segment register (CS): is used fro addressing memory location in the code segment of the memory, where the executable program is stored.
Data segment register (DS): points to the data segment of the memory where the data is stored.
Extra Segment Register (ES) : also refers to a segment in the memory which is another data segment in the memory.
Stack Segment Register (SS): is used fro addressing stack segment of the memory. The stack segment is that segment of memory which is used to store stack data.
While addressing any location in the memory bank, the physical address is calculated from two parts:
- The first is segment address, the segment registers contain 16-bit segment base addresses, related to different segment.
- The second part is the offset value in that segment.
The advantage of this scheme is that in place of maintaining a 20-bit register for a physical address, the processor just maintains two 16-bit registers which is within the memory capacity of the machine.
Pointers and Index Registers.
The pointers contain offset within the particular segments.
- The pointer register IP contains offset within the code segment.
- The pointer register BP contains offset within the data segment.
- He pointer register SP contains offset within the stack segment.
The index registers are used as general purpose registers as well as for offset storage in case of indexed, base indexed and relative base indexed addressing modes.
The register SI is used to store the offset of source data in data segment.
The register DI is used to store the offset of destination in data or extra segment.
The index registers are particularly useful for string manipulation.
Flag Register
The 8086 flag register contents indicate the results of computation in the ALU. It also contains some flag bits to control the CPU operations.
8086 Architecture:
The 8086 architecture supports
- a 16-bit ALU.
- a set of 16 bit registers
- provides segmented memory addressing scheme
- a rich instruction set.
- Powerful interrupt structure
- Fetched instruction queue for overlapped fetching and execution step.
The internal block diagram units inside the 8086 microprocessor is shown in the figure.
FIG
The architecture of 8086 can be divided into two parts
(a) Bus Interface unit (BIU)
(b) Execution unit (EU)
The bus interface unit is responsible for physical address calculations and a predecoding instruction byte queue ( 6 bytes long).
The bus interface unit makes the system bus signal available for external devices.
The 8086 addresses a segmented memory. The complete physical address which is 20-bits long is generated using segment and offset registers, each 16-bits long.
Generating a physical address:
- The content of segment register (segment address) is shifted left bit-wise four times.
- The content of an offset register (offset address) is added to the result of the previous shift operation.
These two operations together produce a 20-bit physical address.
For example, consider the segment address is 2010H and the offset address is 3535H.
The physical address is calculated as: