23-11-2012, 02:25 PM
Overview of VLSI Design Methodologies
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Design Strategies
Design Parameters By Which Design Success Is Measured:
Performance Specs - function, timing, speed, power
Size of Die - manufacturing cost
Time to Design - engineering cost and schedule
Ease of Test Generation & Testability - engineering cost, manufacturing
cost, schedule
Structured Design Strategies
Strategies common for complex harware and software projects.
-> Hierarchy: Subdivide the design into several levels of sub-modules
-> Modularity: Define sub-modules unambiguously & well defined interfaces
-> Regularity: Subdivide to max number of similar sub-modules at each level
-> Locality: Max local connections, keeping critical paths within module
boundaries
LOCALITY
TIME LOCALITY: modules see a common clock and synchronous timing is applied.
-> Robust clock generation and distribution is critical
-> Critical paths, where possible, are to be kept within module boundaries
-> Any global module to module signal should have an entire clock cycle to traverse the chip.
-> Replicate logic, if necessary, to alleviate cross-chip crossings.
-> Locate modules in layout to minimize large or "global" routes between modules.
Field Programmable Gate Array (FPGA)
Fully fabricated FPGA chips containing thousands of logic gates or even more, with programmable interconnects, are available to users for their custom hardware programming to realize desired functionality.
This design style provides a means for fast prototyping and also for cost-effective chip design, especially for low-volume applications.
A typical field programmable gate array (FPGA) chip consists of I/O buffers, an array of configurable logic blocks (CLBs), and programmable interconnect structures.
The programming of the interconnects is implemented by programming of RAM cells whose output terminals are connected to the gates of MOS pass transistors.
Gate Array Design
Programming of the gate array is done with metal mask design and processing.
Gate array implementation requires a two-step manufacturing process:
The first phase, which is based on generic (standard) masks, results in an array of uncommitted transistors on each GA chip.
These uncommitted chips can be stored for later customization, which is completed by defining the metal interconnects between the transistors of the array
Typical gate array platforms allow dedicated areas, called channels, for intercell routing The availability of these routing channels simplifies the interconnections, even using one metal layer only. The interconnection patterns to realize basic logic gates can be stored in a library
While most gate array platforms only contain rows of uncommitted transistors separated by routing channels, some other platforms also offer dedicated memory (RAM) arrays to allow a higher density where memory functions are required
Full Custom Design
In a fuller custom design, the entire mask design is done anew without use of any library. the development cost of such a design style is becoming prohibitively high.
For logic chip design, a good compromise can be achieved by using a combination of different design styles on the same chip, such as standard cells, data-path cells and PLAs.
In real full-custom layout in which the geometry, orientation and placement of every transistor is done individually by the designer, design productivity is usually very low - typically 10 to 20 transistors per day, per designer.