20-09-2012, 01:26 PM
Logarithm and Antilogarithm Computations for Floating point Numbers
Based on Linear Interpolation
Logarithm and Antilogarithm.pdf (Size: 101.33 KB / Downloads: 36)
Abstract
The logarithm number system is an attractive alternative to the conventional number systems when data needs to be manipulated at a very high rate over a wide range This paper presents an approach for hardware realization of elementary functions logarithm and antilogarithm of floating point numbers represented in a similar fashion to IEEE754 format. The need of realizing such functions in hardware is of great value to protect the performance of many applications that includes digital and analog signal processing, computer graphics, multimedia applications etc. our approach is totally based on lookup tables and linear interpolation. The novelty of our approach lies in the fact that multiplication and division involved in interpolation is performed using simple binary addition and subtraction which makes it more efficient. Also the steps involved in computing logarithm and antilogarithm is implemented in a Field programmable gated array (FPGA). Furthermore we also demonstrated how the accuracy varies with the size of lookup table and also compared the simulation results with the actual results.
INTRODUCTION
The speeds associated with the present day electronic applications makes the generation of elementary functions fast enough with more accuracy The logarithm number system (LNS) is an attractive alternative to the conventional number systems when the data needs to be manipulated at a very high rate over a wide range. The LNS can simplify multiplication, division, roots, and powers. When logarithms are used, multiplication and division are reduced to addition and subtraction, respectively, and powers and roots are reduced to multiplication and division, respectively. Logarithm and Antilogarithm are two such functions whose generation is critical to performance in many of the computing applications. Our approach provides a good solution for Field programmable gated array (FPGA) based applications which require high accuracy with less cost. Software based approaches or algorithms for the generation of such elementary functions [1], are not fast enough as stated in.So it is necessary to use a dedicated hardware for these computations.
ARCHITECTURE IMPLEMENTATION
Architecture for Logarithm Implementation
The architecture for the implementation of logarithm function is illustrated in Figure3. The input is expressed in equation (1) format. The input mantissa is restricted to the interval 0 ≤ m < 1. The numbers of bits used to access the LUT depends on the size of it. If the lookup table is of 64 intervals then n=6 bits are used to access the lookup table and if the Look up Table consist 128 entries than n=7. In order to achieve more approximated results the size of the word stored in the LUT is restricted to a minimum of 16 bits.
CONCLUSIONS
The implementation of functions such as logarithm and antilogarithm in hardware is of great value to protect the performance of many applications that includes digital and analog signal processing, computer graphics, multimedia applications etc. In this paper we present the computation of logarithm and antilogarithm for floating point numbers based on linear interpolation. We also implemented these functions on to a FPGA device. In our approach we found accuracy of around 10 bits with lookup tables of size 64 and 128 entries. More accuracy can be obtained just by using the lookup tables with 256 or more entries.