02-11-2012, 11:55 AM
PLACE AND ROUTE AND BACK ANNOTATION
PLACE AND ROUTE.doc (Size: 130 KB / Downloads: 24)
AIM:
To study the place and route and back annotation algorithm for FPGA using 4*1 multiplexer.
APPARATUS REQUIRED:
• XILINX ISE 9.2i software
• PC with Windows-XP
ALGORITHM:
• Create a new verilog file
• Assign port name
• Write verilog HDL code for 4*1 multiplexer.
• Check syntax
• Run place and route tool to assign pin location for each port
• Using view or edit routed design to change the assigned pin locations.
• View the locked pin locations.
THEORY:
It is the translation of routed and fitted design to a timing simulation net list. To define the behavior at the FPGA, a hardware description language or a schematic design automatic [EDA] to technology mapped net list is generated. The net list can then be fitted to the actual FPGA architecture using a process called place & route. Finally the design is said out in FPGA at which point propagation delay can be added and the simulation run again with this value annotated on the net list.