20-09-2012, 04:07 PM
POWER OPTIMIZATION IN RANDOM PATTERN GENERATOR
POWER OPTIMIZATION.ppt (Size: 711 KB / Downloads: 27)
ABSTRACT
Generally LFSR are high correlations are between the consecutive patterns are higher in testing mode it leads to optimize more power. So, the proposed Bit Swapping LFSR for test-per-scan BIST is based upon some new observations concerning the number of transitions produced at the output of an LFSR.
INTRODUCTION
Now a days all the demand for portable computing devices and communications system is increased rapidly. The operational speed of those devices are very high and output is susceptible to environmental conditions. So, every device is need to check while it is running for each and every pattern.
MOTIVATION
During testing mode several methods are proposed to optimize the power but it simultaneously increases the device cost so Bit-Swapping LFSR is proposed with two goals:
Reduce the number of transitions in randomly generated patterns.
Reduce the number of specified bits by generating LFSR seeding.
CONCLUSION
A low transition test pattern generator, called Bit Swapping LFSR is designed to reduce average and peak power of a circuit during test by reducing the transitions within test pattern and between consecutive patterns.