02-01-2013, 10:37 AM
Simplified VHDL Coding of Modified Non-Restoring Square Root Calculator
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ABSTRACT
Square root calculation is one of the most useful and vital operations in
digital signal processing, the operation which in recent generations of
processors is performed by the hardware. The hardware implementation of
the square root operation can be achieved by different means, but it is very
dependent on programmer's sense and ability to write efficient hardware
designs. This paper offers universal and shortest VHDL coding of modified
non-restoring square root calculator. The main principle of the method is
similar with conventional non-restoring algorithm, but it only uses subtract
operation and append 01, while add operation and append 11 is not used. The
strategy has been conducted to implement it successfully in FPGA hardware,
and offer an efficient in hardware resource, and it is superior.
INTRODUCTION
In many VLSI applications, it is an urgent requirement to provide the computation of square root of
a binary coded number with low power dissipation and fast computation (low delay propagation). Square root
calculation is one of the most useful and vital operations in computer graphics and scientific calculation
applications, such as digital signal processing (DSP) algorithms, math coprocessor, data processing and
control, and even multimedia applications [1-6]. It is a classical problem in computational number theory,
which is oftenly encountered and which is a hard task to get an exact result [7-8].
Many square root calculation techniques have been proposed, such as Rough estimation, Babylonian
method, exponential identity, Taylor-series expansion algorithm, Newton-Raphson method, Sweeney
Robertson Tocher redundant and non redundant method, restoring and non-restoring algorithm (digit-by-digit
method) [1-9]. However, the early processors carry out the square root operation of the algorithms above by
software means, which have long delays for its completion [6]. With the rapid advancement of technology
which allows the integration of large circuits on a single chip and the increase in demand for faster
computational execution time, the hardware realization of square root became more attractive [6].
Unfortunately because of the complexity of the square root algorithms, the square root calculation is not easy
to be implemented on Field Programmable Gate Array (FPGA) technology [1, 3, 5, 10].
MODIFIED NON-RESTORING SQUARE ROOT ALGORITHM
Samavi, et al [6] has improved classical non-restoring digit-by-digit square root circuit by
eliminating redundant blocks which still based on constant binary digit of 01 or 11 and adder-subtractor as
the main building block. This paper offers a simple strategy while only uses subtract operation and appends
01. This strategy is implemented by VHDL programming at RTL abstraction.
A hardware implementation of the non-restoring digit-by-digit algorithm for 6-bit unsigned square
root by an array structure is shown in Figure 1. The radicand is P (P5,P4,P3,P2,P1,P0), U (U2,U1,U0) as
quotient and R (R4,R3,R2,R1,R0) as remainder. It can be shown that the implementation needs three-stage
pipelines. The basic building blocks of the array are blocks called Controlled Subtract-Multiplex (CSM).
Figure 2 presents the details of a CSM. The inputs of the building block are x,y,b and u, while ports
bo(borrow) and d (result) are the outputs. If u=0, then d<=x-y-b; else d<=x. For optimizing hardware
resource utilization of the implementation above, specialized entities can be created as building block
components. It will eliminate circuitry that is not needed.
RESULTS AND ANALYSIS
In the previous sections, the hardware implementation of the non-restoring digit-by-digit algorithm for
square root is described. The first observation is conducted to validate the output of the square root
calculation in simulation, which has been performed by using ModelSim-Altera. Then, the results acheived
are reproduced in the hardware test, by observing the ADC system output. The simulation and experiment
result are shown in Figure 5.a and 5.b, respectively.
CONCLUSION
In many VLSI applications, it is an urgent requirement to provide the computation of square root. The
operation is one of the most useful and vital operations in digital signal processing. This paper has presented
a novel strategy of the FPGA implementation of non restoring square root calculator. It has provided a
universal and shortest VHDL coding of modified non-restoring square root calculator, and offers an efficient
in hardware resource, and it is superior.