08-08-2012, 03:31 PM
Pass Transistor Logic
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Complementary Pass-transistor Logic (CPL)
◆ “A 3.8 ns CMOS 16 x 16b Multiplier Using Complementary Pass-
Transistor Logic” by K. Yano etc., IEEE J. of Solid-state Circuits, Vol 15,
No 2, April 1990.
• Logic network employs input signals at both gate and drain terminals.
• Inputs and Outputs are always complementary.
• Outputs from network provide strong ‘0’s but weak ‘1’s. Inverters and
PMOS pull-ups provide amplification and buffering as necessary.
Recent development in PTL
• New development by designers at Hitachi Japan
in the last 6 years.
• Three circuit styles proposed:
➤Complementary Pass-transistor Logic (CPL), 1990
➤Double Pass-transistor Logic (DPL), 1993
➤Lean Integration with Pass-transistors (LEAP), 1996
• All exploit pass-transistors to implement general
logic functions
Lean Integration with Pass-Transistor (LEAP)
◆ “Top-Down Pass-Transistor Logic Design”, K. Yano etc., IEEE J. of
Solid-State Circuits, Vol 31, No. 6, June 1996.
• It eliminated the need for keeping a large cell library by replacing a
library of 61 basic cells with a new set of THREE library cells called Y1,
Y2 and Y3, and 4 inverters of different drive strength.