20-11-2012, 06:11 PM
Performance Analysis of Error Control Codes for Wireless Sensor Networks
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Abstract
In wireless sensor networks, the data transmitted from the sensor
nodes are vulnerable to corruption by errors induced by noisy
channels and other factors. Hence it is necessary to provide a proper
error control scheme to reduce the bit error rate (BER). Due to the
stringent energy constraint in sensor networks, it is vital to use
energy efficient error control scheme. In this paper, we focus our
study on the performance analysis of various error control codes in
terms of their BER performance and power consumption on different
platforms. In detail, error control codes with different constraints are
implemented and simulated using VHDL. Implementation on FPGA
and ASIC design is carried out and the energy consumption is
measured. The error control performance of these codes is evaluated
in terms of Bit Error Rate (BER) by transmitting randomly generated
data through a Gaussian channel. Based on the study and
comparison of the three different error control codes, we identify that
binary-BCH codes with ASIC implementation are best suitable for
wireless sensor networks.
Introduction
The low-cost, rapid deployment, ability of self-organization and
cooperative data-processing, have made wireless sensor networks a
practical solution for a wide range of application areas, including
military and homeland security, health, environment, industry and
commercial, and home [1]. The most significant challenge in sensor
networks is to overcome the energy constraints since each sensor
node has limited energy to consume. Since data transmitted over the
wireless media is vulnerable to corruption by noise, error control
schemes are necessary to keep the Bit Error Rate (BER) low. Due to
the stringent energy constraint, it is impossible to increase the signal
power of the transmitted signal in wireless sensor networks. Hence an
alternative way is to use the error control codes to reduce the BER.
The encoding and decoding circuitry for error control codes may
consume a sizable amount of power. This motivates us to study
energy-efficient error detection/correction codes.
Methodology
In this work, we evaluate the power consumption of three
different FEC codes, BCH, RS, and convolution codes on different
platforms. The implementation on general processors may be
inefficient due to the limitation of the compiler and other factors [8].
Hence, we implement the three codes with different constraints using
hardware description language and estimate their power consumption
on FPGA and ASIC. The code with the least power consumption is
identified. All the comparison is based on the assumption of the same
error control performance which is evaluated by the BER test. In the
following, we explain the methods used in our study.
Implementation of Codes
The three types of error correction codes are implemented using
VHDL. Fig. 1 illustrates the procedure of encoding and decoding in a
communication system, where u is the information word, v is the
codeword, v’ is the received word and u’ is the decoded word. The
encoder circuits of linear block codes and convolutional codes have
simple hardware and are easy to implement. Some of the issues
considered while implementing the decoder circuits are as follows.
Performance Measure
The next step is to measure the error correcting capability of the
implemented codes which is given by BER, which is obtained by the
number of erroneous bits divided by the total number of transmitted
bits. BER is affected by several factors including noise in the
channel, quantization technique used, code rate R, energy per symbol
to noise ratio Es/No and transmitter power level Pout. The code rate is
given by R = k/n, where k is the number of bits at the input of the
encoder and n is the number of bits at the output of the encoder. The
BER is shown to be directly proportional to the code rate and
inversely proportional to energy per symbol noise ratio and
transmitter power level [2].
The encoder encodes the data with code rate R and transmits it
over the noisy channel. If the transmitter power level Pout is
unchanged, then the received energy per symbol E decreases to R*E.
Hence, the BER measured at the input of the decoder is larger than
the BER of the data transmitted without coding [2]. This increase in
BER is overcome by using a decoder that can correct errors. Proper
choice of error correction codes will reduce the BER to several orders
of magnitude. The difference in BER achieved by using error
correction codes to that of uncoded transmission is referred to as
coding gain. The BER test is performed by simulations on Matlab
following the procedure shown in Fig. 1.
Power Estimation in ASIC Design
Power estimation in ASIC is studied using Synopsys’s Design
Compiler (DC) and Design Vision [10]. The power analysis in ASIC
is performed in the following procedure. First the VHDL design is
analyzed to check if it uses the synthesizable VHDL subset. Then the
design is elaborated, where the design is built with generic and
technology-independent components like Gates, Flip Flops, MUX,
etc. It is followed by uniquify, where multiple copies of the subdesign
are made whenever it is referred in the upper level of the
hierarchy, and each copy is optimized in a unique way according to
the conditions and constraints. The last step of synthesis is compiling,
where the network generic components is translated into a netlist of
the target library. Compilation can be constrained in terms of power.
The power report is then generated.
Performance Analysis
In this section, we present and compare the performance of the
binary-BCH, RS codes, and Viterbi codes in terms of their error
correction capability in bit error rate (BER) and complexity and
power consumption on FPGA and ASIC.
Power Analysis in ASIC
Power consumption in ASIC design is obtained as explained in
Section 2. The target library used is lsi_10k.db [10]. Fig. 6 shows the
power consumed by the encoder and decoder circuitry of all three
type of codes in ASIC. It is clear that the power consumption in
binary-BCH and RS codes are directly proportional to the number of
parity bits and the power consumption of the convolutional code is
proportional to the memory order m. Also the power consumed by the
decoder circuit is significantly higher than that consumed by the
encoder circuit of all the codes. The decoding of RS codes and
convolutional codes consume significantly larger amount of power
compared to that of the binary-BCH codes. And the binary-BCH
codes consume the least power among all the codes.