05-07-2013, 12:30 PM
Phase-Locked Loop Circuit Design II
Phase-Locked Loop.ppt (Size: 237.5 KB / Downloads: 20)
Goals:
To design a phase-locked loop (PLL) which can be used for modulation and demodulation of a frequency modulated signal, signal regeneration and clock recovery.
The PLL should compare two signals; the crystal oscillator frequency of the PLL divided by a constant, n, and the output frequency of the VCO. The output frequency should match the PLL crystal oscillator frequency within the lock time. For simulation, the crystal oscillator was replaced by a voltage source with a set frequency.
Overview:
The design of the PLL has four basic components: The frequency divider, phase detector, loop filter, and voltage controlled oscillator (VCO). A basic block diagram follows to illustrate the basic signal flow of the circuit.
Actual circuit design built around digital and analog circuit components such as junction transistors, capacitors and flip flops
Modes of synthesis will be Multisim and PSpice circuit design
packages .
Conclusions/Outcomes:
PLL was able to achieve lock for frequency range from 30MHz to
110 MHz
Set up time for VCO was about 1.01us
PLL will only be in lock for a short amount of time
this is referred to as the ‘hold time.’ After the hold time has expired,
the PLL tends to leave lock to approach the free running frequency of the
VCO. The phenomenon will continue indefinitely.
Our ‘hold time’ turned out to be about 2us.
VCO is most important part of circuit. It provides output as well as
Second signal to be compared to input.