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ABSTRACT
Now a day’s SDR’s are used widely defense and military applications for the purpose
of communication mainly. This offers the advantages on the fly repair, maintenance and
modifications. This project tells the design and implementation of a DQPSK and
reconfigurable SDR based radio transmitter and radio receiver. The experimental presented in
this thesis makes use of system generator DSP, productivity tool from Xilinx to design and
simulate system level model in MATLAB/Simulink environment to obtain BER, spectral
efficiency.
This Project addresses Differential Quadriphase Shift Keying (DQPSK) modulation
implemented on SDR platform for the development of digital data communications based on
Software-Defined Radio (SDR). In my experiment, I used MATLAB tools to generate the
noise sequence, the data rate, the both data and noise sequence and add them together,
recover signal from noisy received data and calculate BER and then plot them with different
SNR values. Here the AWGN noise and channel medium all these noises (which are added)
are nullified using five different algorithms at the receiver end to get the original transmitted
bits (information). In this project designed an SDR to operate at 400MHz frequency (we can
control and modify this frequency range according to the JTRS standard [2MHz to 2GHz]).
INTRODUCTION:
Quadrature Phase-shift keying (PSK) is
a digital modulation scheme that conveys
data by changing, or modulating, the phase
of a reference signal (the carrier wave).
Any digital modulation scheme uses a
finite number of distinct signals to
represent digital data. QPSK uses four
number of phases, each assigned a unique
pattern of binary digits. Each phase
encodes two bits. Each pattern of bits
forms the symbol that is represented by the
particular phase. The demodulator, which
is designed specifically for the symbol-set
used by the modulator, determines the
phase of the received signal and maps it back to the symbol it represents, thus
recovering the original data. This requires
the receiver to
be able to compare the phase of the
received signal to a reference signal —
such a system is termed coherent (and
referred to as CPSK).
Alternatively, instead of operating
with respect to a constant reference wave,
the broadcast can operate with respect to
itself. Changes in phase of a single
broadcast waveform can be considered the
significant items. In this system, the
demodulator determines the changes in the
phase of the received signal rather than the
phase (relative to a reference wave) itself.
Since this scheme depends on the
difference between successive phases, it is
termed differential Quadrature phaseshift
keying (DQPSK). DPSK can be
significantly simpler to implement than
ordinary PSK since there is no need for the
demodulator to have a copy of the
reference signal to determine the exact
phase of the received signal (it is a noncoherent
scheme).
In differentially encoded QPSK (DQPSK),
the phase shifts are 0°, 90°, 180°, −90°
corresponding to data '00', '01', '11', '10'.
Writing the symbols in the constellation
diagram in terms of the sine and cosine
waves used to transmit them:
Design Approach:
The Transmitter and Receiver of DQPSK
modem are simulated on System Generator
(Simulink Matlab). This model can be
synthesised to be used as a Component in
the FPGA after ensuring that the
Simulation is giving the required
parametric results in terms of the symbol
recovery, Symbol Spread, Symbol
convergence time, Carrier Recovery and
true bit recovery. The phase, amplitude
and frequency impairments can be added
to the Test Modulated DQPSK signal
given to the demodulator during
simulation.
The following are the steps involved during
the development process.
MATLAB Simulink (sys.Gen) Fixed
point Implementation of transmitter
and Receiver Transmitter and
Receiver validation.
FPGA Implementation, Simulation
and Testing.
RF Interface and Performance Test.
The DQPSK receiver is targeted for a BER
of 10e-6 BER. An AWGN channel is simulated and the input to the receiver
would have AWGN noise added
transmitted wave.
Five Main Algorithms run in the receive
path to faithfully recover the Transmitted
data at the given BER during the
Demodulation process. The Signal
received would have undergone Phase,
Amplitude impairments in the channel
Medium, AWGN noise too adds up to the
received signal.
These impairments are nullified by the
following algorithms running together.
1. Timing recover Algorithm (Gardner
Timing Recovery).
2. Automatic gain Control.
3. Carrier Frequency Correction algorithm
(Costal loop).
4. Phase imbalance Correction algorithm.
5. Time Domain Equaliser.
INTERPOLATOR CONTROLLER:
The purpose of interpolator control block
is to provide the interpolator with the kth
base point index with m (k) and the kth
fractional interval u (k). The base point
index is usually not computed explicitly
but rather identified by a signal often
called a strobe. The commonly used
method for interpolation control counter
based method.
Modulo-1 counter Interpolation Control:
For the Case where interpolant are
required for every N samples, interpolation
control can be accomplished using a
modulo-1 counter designed to underflow
every N samples where the underflows are
aligned with the base point index.
The counter decrements by 1/N on an
average so that underflows occur every N
samples on average. The loop filter output
v (n) adjusts the amount by which the
counter decrements. This is done to align
the underflows with sample times of the
desired interpolant. The underflow
condition is indicated by a strobe and is
used by the interpolator to identify the
base point index.
The fractional interval may be computed
directly from the contents of module -1
counter on underflow.
The counter value satisfies the recursion:
n (n+1) =(n(n)-W(n)) mod1
Where W (n) =1/N+v (n)
n (m (k)+1)=1+n(m(k))-W(m(k))
1
? (? ) = 1
1
? + ? (? )