29-01-2013, 03:59 PM
Pipelined Architecture with solutions to data & control hazards
Pipelined Architecture.pdf (Size: 1.49 MB / Downloads: 312)
Pipeline Stall
Some stages must by repeated – other invalidated
Reading the register being modified:
the same register can be referred to in ID (read) and in
WB (write) stage – the writing can be done before
(half clock cycle) reading
Software "Pipeline Stall"
Software correction of data flow with NOP (No Operation)
not truly optimization, but might be occasionally necessary
when hardware mechanisms are insufficient
Software Optimization for Architecture
Static: optimization at compilation time
(optimising compiler)
e.g. gcc -On -march=xxx
Dynamic: at run-time: executing instructions in optimal
order detected by hardware
dynamic scheduling
rename registers
out of order execution
speculative execution
Forwarding
Hardware solution to most data hazards
(between EX-MEM, EX-WB stages)
Transfer of most-up-to-date results from
Ex/Mem and Mem/WB to ALU input
Hardware: combinatorial comparators of:
register numbers to be modified
(Ex/Mem.Rd lub Mem/WB.Rd)
● with
register numbers of operands for ALU
(ID/Ex.Rs lub ID/Ex.Rt)
Destination register is always updated in program order
Hardware Pipeline Stall
Detection of hard data hazards must be done early (in ID)
Additional RAW-hazard detection (combinatorial
comparator) block is required in ID
RAW-hazard detection block should be transparent for
both main control and forwarding units
RAW-hazard detects:
LW in stage EX (by examining ID/Ex.MemRead)
conflicting instruction in ID (by opcode: R-type, SW, BEQ)
matching numbers of registers:
● ID/Ex.Rt (LW destination) and
● IF/ID.Rs or IF/ID.Rt (conflicting instruction operands)
Control Hazard
Any jump/branch breaks the natural sequence of
instructions and spoils the pipeline (CPI > 1)
Conditional branches (apart form address calculation)
must also calculate the conditions – it may take time
Jump/Branch execution will require a few following
instructions to be invalidated
Effective solutions:
Early Branch Detection – requires additional hardware
Branch History Table – the best, but still based on guess
Early Branch Detection
Condition (simple) is calculated in ID stage – only one
stage of delay will be introduced (instruction in IF)
Only simple condition is allowed (e.g. comparison),
since the registers must be read from register file
Additional address needed in ID –
dedicated for jump/branch address calculation
Instruction in IF must be invalidated – turned into
NOP (effectively the same as invalidation)
Invalidation in IF stage (→NOP) requires clearing the
IF/ID intermediate register
providing, the NOP bit pattern (opcode + rest) is all 0's