14-05-2012, 02:11 PM
Power-Grid Load Balancing by Using Smart Home Appliances
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INTRODUCTION
Global warming is a major concern nowadays, mostly due
to the increase on greenhouse gases concentration in the
atmosphere. Power plants burning fossil fuel are responsible
for a significant fraction of greenhouse pollutants emission.
Among many issues, the global efficiency of power grid is
limited by the need of providing a sufficient amount of spare
power to face unpredictable demand peaks. Renewable energy
sources (wind, solar plants) cause much lower pollution, but
provide an inherently intermittent supply, thus again resulting
in grid balancing issues. Erratic load imbalances are
compensated, at the supply-side, by a service called
“response”, which involves the use of spare generators. Such
generators usually operate at low-output regimes to provide
back-up capacity, and their efficiency is lower than at fullpower
regimes. This relatively increases the greenhouse gas
emissions. Consequently, there is a growing interest for
demand-side techniques which, by adapting the user’s load to
the grid actual availability, would help in smoothing out
fluctuations in the power requirement.
HARDWARE ARCHITECTURE
Although software implementation of DDC-related
algorithm is not difficult at all, it may require significant
amount of software resources, not necessarily affordable in
the tight economic constraints of home appliances market. In
our work we decided to implement dedicated hardware to
provide basic frequency monitoring functions, letting the
software layer take care of comparison and decision policies.
In [4, 5] the implementation of a microcontroller peripheral
has been described, aimed at allowing white goods network
connectivity (Ultra Low-cost Powerline, ULP
communication).
EXPERIMENTAL RESULTS
In cooperation with Renesas Corporation, the circuit has been
designed and incorporated into the architecture of a standard
microcontroller, and a first test production is under way. To
provide pre-production test, we mapped the DDC/ULP
peripheral onto an Altera FPGA board, connected to the
microprocessor internal busses through a Renesas E6000 realtime,
in-circuit emulator. In Fig. 2(a), a sample frequency log
is reported, together with the DDC comparator output, with
threshold set to 0.1% deviation from the nominal, 50 Hz
value.
CONCLUSIONS
In this paper we introduce a new microcontroller peripheral,
featuring a hardware frequency monitor and aimed at dynamic
demand control implementation. The peripheral embeds
further communication and monitoring functions, suitable for
the development of “intelligent” appliances. Test and
simulations have been carried out to evaluate potential
benefits of the DD-controller in balancing the power grid
load, possibly contributing to reduce global warming effect.