09-07-2012, 11:53 AM
Power Modeling for High Level Power Estimationy
Power Modeling for High Level Power Estimationy.pdf (Size: 808.09 KB / Downloads: 84)
INTRODUCTION
With the advent of portable and high-density
micro-electronic devices, the power dissipation of very
large scale integrated (VLSI) circuits is becoming a
critical concern. Modern microprocessors are hot, and
their power consumption can exceed 30 or 50 Watts.
Due to limited battery life, reliability issues, and pack-
aging/cooling costs, power consumption has become
a more critical design concern than speed and area
in some applications. Hence to avoid problems asso-
ciated with excessive power consumption, there is a
need for CAD tools to help in estimating the power
consumption of VLSI designs.
POWER MACROMODELING
What should a power macromodel look like?
Which features are desirable and which are too ex-
pensive and infeasible? To begin with, it is clear that
a macromodel should be simple to evaluate, other-
wise there would be no advantage in using it and one
might as well perform the analysis at the gate level.
Furthermore, it must apply over the whole range of
possible input signal statistics. Finally, it should con-
sist of a xed template, in which certain parameter
values can be determined by a well-dened and auto-
matic process of characterization, without user inter-
vention. We present a macromodel that has all these
properties.
MODEL ACCURACY EVALUATION
In this section, we report the results of the 4-
dimensional power macromodeling approach on the
ISCAS-85 circuits. We have implemented this ap-
proach and built the power macromodels
(4-dimensional look-up tables) for a number of combi-
national circuits. In order to study the accuracy over
a wide range of signal statistics, we randomly gener-
ated blocks of input vectors at the circuit inputs while
covering a wide range of Pin, Din, and SCin values
that satisfy (18) and (33).
CONCLUSION
Since gate-level power estimation can be
time-consuming and because power estimation from
a high level of abstraction is desirable so as to re-
duce design time and cost, we have proposed a power
macromodeling approach for combinational circuits
with synchronous inputs. Our macromodel consists
of a 4-dimensional look-up table with axes for aver-
age input signal probability, average input transition
density, average input spatial correlation coecient
and average output (zero-delay) transition density.