19-04-2013, 03:20 PM
DESIGN OF 16 BIT MICROPROCESSOR USING VHDL
DESIGN OF 16 BIT.ppt (Size: 855.5 KB / Downloads: 66)
FLOW OF PRESENTATION
VLSI Technology
What is VLSI
Design Flow
Hardware Description Languages
VHDL basics
VLSI
Very Large Scale Integration.
VLSI chips provide:
Compactness,
Low power consumption,
Higher Reliability and speed,
Significant cost savings.
VLSI DESIGN FLOW
System design specification.
Design entry using VHDL or Verilog.
Logic Synthesis and verification.
Circuit design and testing.
Physical layout design and verification.
Manufacturing, testing and packaging.
Final VLSI chip
VHDL BASICS
Very high speed integrated circuit Hardware Description Language.
It is being used for documentation, verification, and synthesis of large digital designs.
It employs the structural, data flow, and behavioral methods of hardware description.
An Entity declaration provides the complete input - output interface for a circuit
An Architecture describes the function and structure of a circuit
DESIGN PARAMETERS
16 bit Address and Data bus.
16 bit ALU.
16 bit Control unit, the heart of microprocessor.
Comparator to perform logical operations.
16 bit Register array for temporary storage of data.
Address register to point the current instruction.
Program counter to point the next instruction.
Instruction register to store the fetched instruction code.
Operation register .
Shift unit to perform Shift and rotate operations.
Out register for temporary storage of data.
OPERATION CYCLE OF MICROPROCESSOR
Reset is kept high for 1 clock cycle. So that reset cycle starts, output 0000h will be placed on address bus and data bus.
The data from data bus gets copied in address and program counter register.
Now, VMA goes high and WRB goes low.
Then if READY is high, the data on data bus will get stored in instruction register.
Control unit takes first 5 bits (15 downto 11) from instruction register to decode the type of operation.
Now first decoded instruction is executed.
Finally procedure of incrementing program counter starts. And then whole cycle repeats.