11-10-2012, 11:09 AM
Power Switch-off Technique
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ABSTRACT
Low power or power efficiency is a key design requirement for nanometer designs today. The market for consumer and wireless devices is rapidly changing, driven by the convergence of applications, standards, and usage. Complexity challenges are forcing these devices to be designed at 90nm and below geometries where transistor leakage is increasing exponentially. In order for these devices to deliver additional functionality without compromising on form factor or battery life, they need to employ aggressive leakage power reduction (>20X). Logic modules must be shut down when they are not required in operation. Power gating is emerging as the technique to address this complex challenge.
Power gating, or power switch-off technique, usually refers to placing switches on-chip to selectively turning off current supply based on the application requirement. Designers are employing two types of power gating - fine-grain power gating and coarse-grain power gating.