09-04-2012, 03:05 PM
Processor with Integrated DRAM Main Memory
xu-zhang.ppt (Size: 682 KB / Downloads: 458)
Von-Neumann Model
Semiconductor industry divides into microprocessor and memory camps
Separate chips, separate packages
Memory size is bigger but low power cost
CPU speed is faster and high power cost
Desktop: 1~2 CPU, 4~32 DRAMs
Server: 2~16 CPU, 32~256 DRAMs
Disadvantages of Von-Neumann Model
Performance gap: CPU (60% each year) vs. DRAM (7% each year)
Memory Gap Penalty: larger caches (60% on-chip area, 90% transistors)
Caches are purely performance enhancement mechanisms…. Correctness does not depend on them
No. of DRAM chips shrinking for PC config
In future it maybe a single DRAM chip
The required min. memory size, means application and OS memory use, grows only 50~75% of rate of DRAM capacity
Limitation of Present Solutions
Huge cache:
Slow and works well only if the working set fits cache and there is some kind of locality
Prefetching
Hardware prefetching
Cannot be tailored for each application
Behavior based on past and present execution-time behavior
Software prefetching
Ensure overheads of prefetching do not outweigh the benefits
Hard to insert prefetches for irregular access patterns
SMT
Enhance the utilization and throughput at thread level
Conclusion
The trend towards larger DRAM devices exacerbates the processor / memory bottleneck, requiring costly cache hierarchies to effectively support high performance microprocessors.
A viable alternative is to move the processor closer to the memory, by integrating it onto the DRAM chip.
Processor / memory integration is advantageous, even if it requires the use of a simpler processor.