26-12-2012, 04:28 PM
Programmable ASICs
Programmable ASICs.ppt (Size: 312 KB / Downloads: 103)
INTRODUCTION
Two basic types of programmable ASICs
Programmable Logic Device (PLD) - first developed as small programmable devices that can replace a handful of TTL parts
least complex ones are a simple AND/OR PLA with latches on the outputs and feedback paths to the inputs of the array
Field Programmable Gate Array (FPGA) - more complex devices that can hold up to 100K gate equivalents or more
some implemented as symmetrical arrays of simple logic devices
others include more complex and specialized logic blocks
An FPGA (or PLD) is an IC that is fabricated with some connections missing
The user (designer) creates a design to be placed on the FPGA using design entry and simulation
Automatic tools create a string of bits (a configuration file) describing the extra connections necessary to program the FPGA to perform the required function
A device programmer is then (usually) used to load the configuration file into the FPGA
FPGA Components
FPGAs have several basic components:
Regular array of basic (programmable) logic cells
Level of complexity and number of different types of logic cells differs across manufactures and even across families from the same manufacturer
Programmable interconnect for connecting the basic cells into different configurations
Programming technology for configuring the cells and programmable interconnect
One-time-programmable (OTP)
Erasable
Programmed on power-up
Custom software used by the designer to create the configuration file
Programming Technology - the Antifuse
An antifuse is normally open
A high programming voltage is placed across it
This forces a programming current (about 5 mA) through it which melts the thin insulating dielectric forming a permanent, resistive silicon link
Actel Antifuses
Actel antifuse technology uses three additional masks over a traditional CMOS process
Programming an ACTEL device requires about 5 to 10 minutes per device
Production programming of more than 1000 or 2000 devices per week requires a gang (multiple device) programmer
Quicklogic Metal-Metal Antifuse
Metal-metal antifuses directly connect metal wiring layers - thus eliminating the parasitics of a polysilicon layer in between
Direct connections to the metal layers make it easier to use larger programming currents producing a lower antifuse resistance
Configuration via Static RAM
Configuration data is loaded into static RAM on chip
Static RAM cells control pass transistors which configure the logic cells and interconnect
FPGA can easily be reconfigured, even on the fly
Power must be maintained to the chip to retain the configuration or the configuration can be loaded from a PROM on power-up (usually serially)
Using FPGAs
Changing demands from large FPGA users can often result in supply problems
This is less of a problem in MGA or CBIC ASICs as this is arranged directly between the customer and foundry - although a shortage in ASIC foundry capacity is predicted in the future
Most FPGAs are intended for direct placement into a PCB and are thus surface mount devices
Unlike standard PLD devices (e.g. 22V10), FPGA signal and power pinouts vary widely among vendors
Replacing an FPGA with an MGA or CBIC can be difficult because of this and may require pin or I/O locking