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Introduction
Digital Light Processing is the one of primary display technologies driving this
rapid growth and maturation .it is a revolutionary way to project and display information based
on the Digital Micro Mirror Device (DMD) Digital Light processing was invented in 1987 by
Texas Instruments it creates the final link to display digital visual information.
Digital Light Processing creates deeper blacks, conveys fast moving images very well and uses a
single, replaceable, white -light bulb . it is available in both front-and rear-projection models
DLP is an excellent choice for people who watch a lot of sports or fast-action movies because of
the speed at which it creates an image.
DLP Structure
A Digital Micro Mirror Divice chip is the heart of Digital Light Processing
projector, DMD can be described simply as a semiconductor light switch. The micro mirrors are
mounted on the DMD chip and it tilts in response to an electrical signal. The tilt directs light
toward the screen, or into a "light trap" that eliminates unwanted light when reproducing blacks
and shadows. Other elements of a DLP projector include a light source, a colour filter system, a
cooling system, illumination and projection optics.
A DLP based projector system includes memory and signal processing to support a fully digital
approach. Depending on the application, a DLP system will accept either a digital or analog
signal. Analog signals are converted into digital in the DLPs front –end processing. Any
interlaced video signal is converted into an entire picture frame video signal through
interpolative processing. The signal goes through DLP video processing and becomes
progressive Red ®, Green (G) and Blue (B) data. The progressive RGB data is then formatted
into entire binary bit planes of data.
DMD MODULATOR
The DMD modulator is a semiconductor light switch consisting of an array of
micromechanical, individually addressable mirrors built over a single crystal silicon Static
Random Access Memory backplane. Thousands of tiny, square mirrors, fabricated on hinges
atop a static random access memory (SRAM), make up a DMD. Each mirror is capable of
switching a pixel of light. The hinges allow the mirrors to tilt between two states, +10° for ‘on’
or -10 ° for ‘off’. When the mirrors are not operating, they sit in a ‘parked’ state at 0°.
The DMD chip is comprised of over one million mirrors. The size of each mirror
is less than 1/5" the width of a human hair. The DMD is monolithically fabricated by
Complementary Metal Oxide Semiconductor-like processes over a CMOS memory. Each light
switch has an aluminum mirror, 16 µm² that can reflect light in one of two directions depending
on the state of the underlying memory cell. Rotation of the mirror is accomplished through
electrostatic attraction produced by voltage differences developed between the mirror and the
underlying memory cell. With the memory cell in the on (1) state, the mirror rotates to +10°,
with the memory cell in the off (0) state, the mirror rotates to -10°.
The mechanical portion of each pixel consists of a three layer structure. The
center layer, called beam layer, is suspended over the bottom electrode layer by thin torsion
hinges. The top mirror layer is attached to the beam layer with a via post. The yoke may rotate
about the torsion hinge axis to either side, landing on the electrode layer at specific tilt angles of
+/- 10 degrees. Manipulation of the mirrors is accomplished electro statically utilizing the
address electrodes on either side of the torsion hinge. These address electrodes are tied to the
SRAM cell residing in the silicon backplane beneath each mirror structure.
The DMD pixel is a monolithically integrated MEMS superstructure cell fabricated over
a CMOS SRAM cell. An organic sacrificial layer is removed by plasma etching to produce air
gaps between the metal layers of the superstructure. The air gaps free the structure to rotate about
two compliant torsion hinges. The mirror is rigidly connected to an underlying yoke. The
yoke, in turn, is connected by two thin, mechanically compliant torsion hinges to support posts
that are attached to the underlying substrate. The address electrodes for the mirror and yoke are
connected to the complementary sides of the underlying SRAM cell.
The yoke and mirror are connected to a bias bus fabricated at the metal-3 layer. The bias bus
interconnects the yoke and mirrors of each pixel to a bond pad at the chip perimeter. The DMD
mirrors are 16 µm² and made of aluminum for maximum reflectivity. They are arrayed on 17 µm
centers to form a matrix having a high fill factor (~90%). The high fill factor produces high
efficiency for light use at the pixel level and a seamless (pixilation-free) projected image.
Electrostatic fields are developed between the mirror and its address electrode and
the yoke and its address electrode, creating an efficient electrostatic torque. This torque works
against the restoring torque of the hinges to produce mirror and yoke rotation in the positive or
negative direction. The mirror and yoke rotate until the yoke comes to rest (or lands) against
mechanical stops that are at the same potential as the yoke. Because geometry determines the
rotation angle, as opposed to a balance of electrostatic torques employed in earlier analog
devices, the rotation angle is precisely determined.
The fabrication of the DMD superstructure begins with a completed CMOS memory circuit. A
thick oxide is deposited over metal-2 of the CMOS and then planarized using a chemical
mechanical polish (CMP) technique. The CMP step provides a completely flat substrate for DMD superstructure fabrication, ensuring that the projector's brightness uniformity and contrast
ratio are not degraded.
Through the use of six photomask layers, the superstructure is formed with layers of
aluminum for the address electrode (metal-3), hinge, yoke and mirror layers and hardened photoresist
for the sacrificial layers (spacer-1 and spacer-2) that form the two air gaps. The aluminum
is sputter-deposited and plasma-etched using plasma-deposited SiO2 as the etch mask. Later in
the packaging flow, the sacrificial layers are plasma-ashed to form the air gaps. The packaging
flow begins with the wafers partially sawed along the chip scribe lines to a depth that will allow
the chips to be easily broken apart later.
The partially sawed and cleaned wafers then proceed to a plasma etcher that is used to
selectively strip the organic sacrificial layers from under the DMD mirror, yoke, and hinges.
Following this process, a thin lubrication layer is deposited to prevent the landing tips of the
yoke from adhering to the landing pads during operation. Before separating the chips from one
another, each chip is tested for full electrical and optical functionality by a high-speed automated
wafer tester.