24-11-2012, 03:47 PM
INSRUCTION HAZARDS
INSRUCTION HAZARDS.pptx (Size: 483.55 KB / Downloads: 87)
Stream of instructions supplied by instruction fetch unit is interrupted, the pipeline stalls.
Branching Hazards
Branch instruction affects instruction flow
Do not know next instruction to be executed until branch outcome known
When we hit a branch instruction
Need to compute target address (where to branch)
Resolution of branch condition (true or false)
Might need to ‘flush’ pipeline if other instructions have been fetched for execution
Conditional Braches
Added hazard caused by dependency of the branch condition on the result of a preceding instruction.
Decision to branch cannot be made until the execution of that instruction has been completed.
~20% of dynamic instruction count of most programs.
Four Branch Hazard Alternatives
Stall until branch direction is clear – flushing pipe
Predict Branch Not Taken
Execute successor instructions in sequence
Advantage of late pipeline state update
47% branches not taken on average
PC+4 already calculated, so use it to get next instruction
Predict Branch Taken
53% branches taken on average
Delayed Branch
Where to get instructions to fill branch delay slot?
Before branch instruction
From the target address: only valuable when branch taken
From fall through: only valuable when branch not taken
Cancelling branches allow more slots to be filled
Compiler effectiveness for single branch delay slot:
Fills about 60% of branch delay slots
About 80% of instructions executed in branch delay slots useful in computation
About 50% (60% x 80%) of slots usefully filled
Delayed Branch downside: 7-8 stage pipelines, multiple instructions issued per clock (superscalar)
Conclusion
Two features have been introduced
Pipelining operation
Superscalar operation
Potential performance can be realized by paying attention to
Instruction set of the processor
The design of the pipeline hardware
The design of the associated compiler