20-03-2014, 11:25 AM
Traffic Control System
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Introduction:
Verilog
As ASICs have become more complex, other design-entry
methods are becoming common. Alternative design-entry methods
can use graphical methods, such as a schematic, or text files, such
as a programming language. Using a hardware description
language ( HDL ) for design entry allows us to generate netlists
directly using logic synthesis . Verilog VHDL is an accepted IEEE
standard.It has evolved as a standard hardware description
language.
[b]Design System:[/b]
Design entry. Enter the design into an ASIC design system, either
using a hardware description language ( HDL ) or schematic
entry. Steps 1–4 are part of logical design , and steps 5–9 are part
of physical design . There is some overlap. For example, system
partitioning might be considered as either logical or physical design.
To put it another way, when we are performing system partitioning
we have to consider both logical and physical factors.
The Objective of the Project:
The objective of the project is to design a
traffic control system for a 3 way crossing. Here a highway, a railway
and a country way cross each other. In our design, the railway would
have the highest priority. Any moment a train arrives the crossing it
would have a ‘GO’ signal. The other two roads, Highway and Country
Road would have a ‘STOP’ signal at that moment. When there is no
train on the crossing and there are vehicles on the country road to
cross the highway; highway would have a ‘STOP’ signal and Country
Road Vehicles would have a ‘GO’ signal. But it depends on Highway
traffic density. It highway traffic density is high then Country road
would not get a ‘GO’ signal, highway vehicles would keep going.
Traffic Signal processing:
The traffic signal for railway gets highest priority because train
would normally not stop in the road. When a train arrives other
two signals of the country road and highway turns RED. Train
arrival signal is denoted by signal y. When y=1, that expresses
an arrival of a train in the crossing.
Occasionally, cars arrive from country road at the traffic signal.
The 1 bit sensor for car arrival is represented by x. When x=1
then there are cars waiting in the country road for crossing. But
it depends on the pressure of the highway traffic.
Details of the tools selected:
Verilog
HDL:
The
Hardware
Description
Language
Verilog®
originated in 1983 at Gateway Design Automation, and since then it
gained acceptance from designers for simulating large digital circuits.
It offers many useful for hardware design.
It is a general purpose hardware description language that is
easy to learn and use.
It allows different levels of abstraction to be mixed in the same
model. Thus, a designer can define a hardware model in terms
of switches, gates, RTL, or Behavioral code.
Most popular logic synthesis tools support Verilog HDL.
All fabrication vendors provide Verilog HDL libraries for post
logic synthesis simulation. Thus designing a chip in Verilog
HDL allows the widest choice of vendors.
Designers can customize a Verilog HDL simulator to their
needs with the PLI.